Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-08-30
2004-03-23
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000, C438S108000, C257S737000, C257S772000, C257S780000, C257S782000
Reexamination Certificate
active
06709964
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to solder joints that physically and electrically connect a package and a substrate.
2. Description of the Related Arts
The trends for semiconductor integrated circuit (IC) chips have been toward higher density of devices, higher speed, smaller area, and thinner thickness. In keeping with these trends, packages for IC chips therein have moved from pin insert or through hole mount packages to surface mount packages to improve the mounting density on a substrate or circuit board. A Chip Size Package (CSP), for example, permits high mounting density. The CSP offers many advantages. The most obvious advantage is size of the CSP, which is nearly that of the bare chip.
A Wafer Level CSP (WL-CSP) is a kind of the CSP, where packaging processes are predominantly performed on wafers rather than individual chips. Each chip has an array of terminals, typically solder balls, on a face of the chip. The solder balls are rerouted or redistributed from associated chip pads during a wafer fabrication process. Flip chip assembly can attach the chip or die of the WL-CSP to a substrate or circuit board via the solder balls.
The mounting structure using the solder balls has reliability problems at the solder joints. As well known in the art, the chip and the substrate have dissimilar Coefficients of the Thermal Expansion (CTEs). Due to the dissimilarity of the CTEs, changes in temperature create shearing stresses on the solder joints. The shearing stresses often cause cracks or delamination at the solder joints. Temperature Cycling (T/C) testing, which periodically varies the temperature of a chip within a temperature range, for example, from −25° C. to 125° C., can identify problems or defects at the solder joints.
One approach to reducing the reliability problems is the underfill encapsulation method. This method uses a liquid resin encapsulant on the substrate around the chip to fill a gap between the package and the substrate after the flip chip assembly. The underfill encapsulation improves the reliability of the solder joints. However, the underfill encapsulation can introduce new failures. Further, the underfill encapsulation requires additional process steps and thereby increases production cost.
FIGS. 1A and 1B
illustrate how a solder joint can develop cracks, and
FIGS. 2A and 2B
illustrate how the underfill encapsulation prevents such cracks. As shown in
FIG. 1A
, a solder joint
30
bonds a chip size package
10
to a substrate
20
. The solder joint
30
is formed by bonding a solder ball on a ball pad
12
to a substrate pad
22
of the substrate
20
. Alternatively, the solder ball may initially be on the substrate pad
22
and then bonded to the ball pad
12
.
The solder joint
30
cracks easily. Due to the dissimilarity of the CTEs of the chip
10
′ and the substrate
20
, a shearing stress F
1
acts on the top and bottom of the solder joint as shown in
FIG. 1B
, and the resulting deformation can exceed an elastic range of the solder joint. This deformation is often referred to as a “plastic strain”. Repeated changes in the temperature cause the plastic strain to accumulate on the solder joint
30
until the plastic strain exceeds the critical point of the solder, and the solder joint cracks. The crack is often called a “fatigue crack”.
As shown in
FIG. 2A
, if the gap between the package
10
and the substrate
20
is filled, the shearing stress is distributed over the underfill encapsulant
40
. Therefore, the shearing stress F
2
causing the deformation of the solder joint
30
is smaller, and the deformation of the solder joint
30
typically remains within the elastic range. (This deformation is commonly referred to as an “elastic strain”.) The plastic strain, if any, is insignificant. Although the temperature change is repeated, the deformation of the solder joint
30
is not enough to crack the solder joint
30
. Although the underfill encapsulation improves the reliability of the solder joints, the underfill encapsulation can introduce new failures.
FIG. 3
illustrates how an underfill encapsulant
40
such as an epoxy resin not only fills the gap between the package
10
and the substrate
20
, but also supports the side surface of the package
10
. Therefore, the underfill encapsulant
40
fixes the package
10
to the substrate
20
. If the solder joint with the underfill encapsulant undergoes the severe temperature change, the dissimilarity of the CTEs can warp the package
10
and the substrate
20
. Occasionally, this warping causes damage such as a crack
42
in the chip
10
′, a crack
44
in the underfill encapsulant
40
, a delamination
46
at the interface between the package
10
and the underfill encapsulant
40
, or a delamination
48
at the interface between the underfill encapsulant
40
and the substrate
20
.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, a structure and a fabrication method for solder joints in chip size packages reduce fabrication costs, improve the reliability of the solder joints, and prevent other failures.
One embodiment of the present invention is a semiconductor device package that includes an integrated circuit chip, a substrate, a plurality of solder joints, and a stress-relieving film. The integrated circuit chip has a plurality of chip pads and a plurality of ball pads rerouted from the chip pads. The substrate includes a plurality of substrate pads thereon, each substrate pad corresponding to a respective one of the ball pads. Each of the solder joints physically and electrically connects a ball pad to the corresponding substrate pad. The stress-relieving film lies away from and between the package and the substrate. The stress-relieving film is joined to the solder joints to distribute stress in the solder joints over the stress-relieving film.
In one embodiment, the stress-relieving film is a polyimide film and has a plurality of via holes or a plurality of intervenient metal regions corresponding to the solder joints. The solder joints are formed through the via holes or by attaching solder balls to the intervenient metal regions.
In accordance with another aspect, the present invention provides a method for manufacturing a semiconductor device. One embodiment of the manufacturing method includes: (A) providing a package having a plurality of solder balls on the respective ball pads, (B) providing a substrate including a plurality of substrate pads thereon, each substrate pad corresponding to a respective one of the ball pads, (C) positioning a stress-relieving film away from and between the package and the substrate, and (D) reflowing the solder balls to form a plurality of solder joints. Each solder ball physically and electrically connects the corresponding ball and substrate pads. The stress-relieving film attaches to the plurality of solder joints and distributes stress away from the solder joints.
The stress-relieving film can include a plurality of via holes or a plurality of intervenient metal regions, and the solder joints pass through the via holes or attach to the intervenient metal regions. Solder balls can also be formed on the corresponding substrate pads, and reflowing the solder balls on the substrate pads and the solder balls on the ball pads forms the solder joints. In this case, the stress-relieving film is on the substrate, with each solder ball of the substrate pad aligned with a corresponding one of the via holes or metal regions. The package is placed on the stress-relieving film so that each solder ball on the ball pad is aligned with a corresponding one of the via holes or metal pads. When the substrate is without the solder balls on the substrate pads, a fixing means fixes or hold the stress-relieving film away from the substrate by a designated distance.
REFERENCES:
patent: 4878611 (1989-11-01), LoVasco et al.
patent: 4897918 (1990-02-01),
Harness & Dickey & Pierce P.L.C.
Lu Chuong Anh
Samsung Electronics Co,. Ltd.
Smith Matthew
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