Semiconductor device and manufacturing method thereof

Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region

Reexamination Certificate

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C438S528000, C438S554000, C438S585000, C438S586000, C438S595000, C257SE51005, C257SE29130

Reexamination Certificate

active

07838401

ABSTRACT:
A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so as to be offset from the front edge of a source/drain extension in direction away from the gate electrode and to surround as profile the associated source/drain impurity diffusion region.

REFERENCES:
patent: 6153920 (2000-11-01), Gossmann et al.
patent: 7122435 (2006-10-01), Chidambaram et al.
patent: 2005/0095765 (2005-05-01), Saiki et al.
patent: 2006/0134872 (2006-06-01), Hattendorf et al.
patent: 2006/0216900 (2006-09-01), Wang et al.
patent: 2005-136351 (2005-05-01), None
M. Togo et al., “Power-aware 65 nm Node CMOS Technology Using Variable VDD and Back-bias Control with Reliability Consideration for Back-bias Mode”; 2004 Symposium on VLSI Technology, Digest of Technical Papers, pp. 88-89, 2004.

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