Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-18
2001-03-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S210000, C438S238000, C438S329000, C438S396000
Reexamination Certificate
active
06204104
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a capacitor, a bipolar transistor and complementary metal—oxide—semiconductor field effect transistors (MOSFET) and a manufacturing method thereof.
2. Description of the Prior Art
Recently, there has been a demand to add a still larger capacitance to a Bi—CMOSLSI in which complementary metal-oxide-semiconductors (CMOS) marked by large scale integration and low power consumption, as well as a bipolar transistor marked by rapid performance, are formed upon a single semiconductor substrate.
In Japanese Patent Application Laid-open No. 22054/1989, there is disclosed a manufacturing method of a capacitor in a semiconductor device having a MOSFET and a bipolar transistor on a single substrate. In this method, one electrode of the capacitor is formed simultaneously with a gate electrode of the MOSFET, and, after insulating films of the capacitor are formed, an opposite electrode of the capacitor is formed simultaneously with an emitter electrode of the bipolar transistor. The device herein has a structure in which capacitor insulating films are sandwiched by the overlying and underlying electrodes of the capacitor.
However, the capacitor formed in this method occupies a large area, which restricts a large scale integration of the LSI.
Further, in Japanese Patent Application Laid-open No. 291262/ 1994, there is disclosed a method of adding a capacitor with high precision to a Bi—CMOS, wherein a lower electrode of the capacitor is formed over an insulating film and concurrently serves as polysilicon to form gate electrodes of MOSs, while an opposite electrode of the capacitor serves as polysilicon to form a base or an emitter. Nevertheless, this method also has a problem that the capacitor occupies a rather large area.
Meanwhile, as a method of providing a large capacitance without requiring a large area for that, there is, for example, disclosed in Japanese Patent Application Laid - open No. 150955/1988. In this method, as shown in
FIG. 19
(
a
), a polysilicon layer
53
is placed as an intermediate layer. Sandwiching a silicon dioxide film
51
, this polysilicon layer
53
and a diffusion region
52
which is set in an epitaxial layer
57
lying over a silicon substrate
56
form a first capacitor. The polysilicon layer
53
and an Al film
54
, sandwiching a silicon dioxide film
58
, form a second capacitor. The diffusion region
52
and the Al film
54
are connected with each other by means of a contact made through the silicon dioxide film. Accordingly, as shown in
FIG. 19
(
b
), two capacitors are connected in parallel between an Al film
55
brought from the polysilicon layer
53
and the Al film
54
so that a larger capacitance value can be attained.
However, the silicon dioxide film
58
is a part called as an interlayer insulating film and its film thickness is substantial, which causes a problem that a sufficiently large capacitance cannot be necessarily obtained. Moreover, a resistance of the polysilicon layer section becomes relatively large, resulting in another problem of poor high-frequency characteristics thereof.
Further, another capacitor structure formed on a semiconductor substrate, as shown in
FIG. 20
(
a
), is disclosed in Japanese Patent Application Laid-open No. 75021/1993. In this structure, upon a p —type semiconductor substrate
100
, an n-type epitaxial layer
102
is layered, and, over that, an n
+
-diffusion layer
104
is formed. A dielectric layer
106
of silicon dioxide is then formed and a conductive layer
108
of polysilicon is layered in a region where a capacitor is to be formed. Next, a dielectric layer
110
of polysilicon is formed and, after applying a phosphorus glass (PSG) layer
112
, a conductive layer
114
of aluminium is layered to connect with an electrode A. The conductive layer
114
of aluminium also connects with an n
+
-diffusion layer through a contact hole and consequently to an electrode B. Accordingly, a capacitor C
1
with the dielectric layer
106
and a capacitor C
2
with the dielectric layer
110
are connected in parallel so that a capacitance thereof becomes C
1
+C
2
, as shown in
FIG. 20
(
b
).
However, the application of this structure to a Bi-CMOS was not described at all in this prior art. Therefore an efficient manufacturing method for a practical use has been kept unknown. Further, this structure gives rise to a problem of poor high-frequency characteristics since a resistance value of the polysilicon section becomes large.
SUMMARY OF THE INVENTION
In light of the above problems, an object of the present invention is to provide a method of manufacturing, with a high efficiency and a low cost, a semiconductor device such as a Bi-CMOS and the like, which is capable of large scale integration and has a capacitor with a large capacitance and occupying only a small area.
Another object of the present invention is to provide a semiconductor device, such as a Bi-CMOS and the like, which has a capacitor structure having a large capacitance and a low resistance but occupying only a small area and is capable of large scale integration and marked by a rapid response and a good high-frequency characteristics and a manufacturing method thereof.
In accordance with an aspect of the present invention, there is provided a first method of manufacturing a semiconductor device having a capacitor, a bipolar transistor and complementary MOSFETs on a semiconductor substrate, the capacitor comprising a first electrode, a second electrode separated from the first electrode by an insulating film and a third electrode separated from the second electrode by an insulating film and connected to the first electrode; which comprises the steps of:
forming the first electrode simultaneously with forming gate electrodes of the MOSFETs;
forming the insulating film between the first electrode and the second electrode simultaneously with forming an insulating film which prevents source—drain regions of the MOSFETs and a collector bring-out region of the bipolar transistor from being etched, when a base electrode is worked into shape by etching;
forming the second electrode simultaneously with forming a base electrode of the bipolar transistor;
forming the insulating film between the second electrode and the third electrode simultaneously with forming an insulating film which insulates between a base electrode and an emitter electrode of the bipolar transistor; and
forming the third electrode simultaneously with forming the emitter electrode of the bipolar transistor.
In accordance with another aspect of the present invention, there is provided a second method of manufacturing a semiconductor device having a capacitor, a bipolar transistor and complementary MOSFETs on a semiconductor substrate, the capacitor comprising a first electrode, a second electrode separated from the first electrode by an insulating film, a third electrode separated from the second electrode by an insulating film and connected to the first electrode and a fourth electrode formed in the semiconductor substrate, separated the first electrode by an insulating film and connected to the second electrode; which comprises the steps of:
forming the fourth electrode simultaneously with forming a collector electrode of the bipolar transistor;
forming the first electrode simultaneously with forming gate electrodes of the MOSFETs;
forming the insulating film between the first electrode and second electrode simultaneously with forming an insulating film which prevents source -drain regions of the MOSFETs and a collector bring -out region of the bipolar transistor from being etched when a base electrode is worked into shape by etching;
forming the second electrode simultaneously with forming a base electrode of the bipolar transistor;
forming the insulating film between the second electrode and the third electrode simultaneously with forming an insulating film which insulates between a base electrode and an emitter electrode of the bipolar transist
Lattin Christopher
NEC Corporation
Niebling John F.
Sughrue Mion Zinn Macpeak & Seas, PLLC
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