Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-01-29
2008-01-29
Smith, Zandra V. (Department: 2809)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S229000, C257S412000
Reexamination Certificate
active
11180657
ABSTRACT:
A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of an n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide (HfO2) film. Also, the gate electrode of the n channel MIS transistor is composed of an Ni (nickel) silicide film, and the gate electrode of the p channel MIS transistor is composed of a Pt (platinum) film. In this structure, Fermi level pinning of the gate electrodes can be prevented. Therefore, the increase of the threshold voltage of the n channel MIS transistor and the p channel MIS transistor can be inhibited.
REFERENCES:
patent: 6043157 (2000-03-01), Gardner et al.
patent: 6083836 (2000-07-01), Rodder
patent: 6475908 (2002-11-01), Lin et al.
patent: 6727129 (2004-04-01), Nakajima
patent: 6750519 (2004-06-01), Lin et al.
patent: 6815285 (2004-11-01), Choi et al.
patent: 6967379 (2005-11-01), Matsuo
patent: 7105394 (2006-09-01), Hachimine et al.
patent: 2002/0076886 (2002-06-01), Rotondaro et al.
patent: 2003/0092285 (2003-05-01), Hinoue et al.
patent: 2003/0218223 (2003-11-01), Nishiyama et al.
patent: 2004/0065930 (2004-04-01), Lin et al.
patent: 2004/0080001 (2004-04-01), Takeuchi
patent: 2004/0084734 (2004-05-01), Matsuo
patent: 2004/0087070 (2004-05-01), Nakajima
patent: 2005/0260810 (2005-11-01), Cheng et al.
patent: 2004-152995 (2002-10-01), None
patent: 2004-158593 (2002-11-01), None
Hobbs et al., “Fermi-Level Pinning at the Polysilicon/Metal Oxide Interface—Part I”, IEEE Transactions of Electron Devices, vol. 51. No. 6, Jun. 2004, pp. 971-984.
Kadoshima Masaru
Nabatame Toshihide
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Green Telly
Reed Smith LLP
Smith Zandra V.
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