Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2002-12-18
2004-08-31
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S737000, C257S741000, C257S773000, C257S690000
Reexamination Certificate
active
06784554
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device having an Si chip mounted on a wiring substrate in a face down manner by way of noble metal bumps and a mounting method thereof and, more particularly, it relate to a chip/substrate bonding structure, a metallized constitution of bonding terminals and a metal bonding method capable of reducing chip damages upon mounting and greatly improving the heat resistance, the temperature cycle life, as well as high temperature-high humidity and high temperature maintaining reliability.
Existent flip chip mounting methods for semiconductor chips using Au bumps includes, for example,
(1) Au/Au direct bonding,
(2) Au/Au contact connection by chip adhesion with an insulative resin,
(3) Au/Ag grain/Au contact connection by chip adhesion with an anisotropically conductive resin,
(4) Au/Sn melt bonding.
In the contact connection system by resin adhesion (2) and (3), degradation is remarkable in various kinds of reliability tests after exposure to a high humidity circumstance and reliability is poor. In the melt bonding system using the low melting metal (4) and brittle intermetallic compounds are formed on the bonding boundary, tending to cause cracks in the course of cooling after bonding or during a temperature cycle test to lower the strength reliability. At present, a mounting method of most excellent reliability is the Au/Au direct bonding method.
In the existent technique of the Au/Au bonding system, a method of mounting a surface wave device formed with Au bumps in a face down manner on an Au pad of a wiring substrate by metal bonding under application of supersonic waves is disclosed as the prior art in Japanese Patent Laid-open Hei 10-107078 and in the technical report of Electronic Communication Society (July, 1995). In the prior art described above, for reliable metal bonding between an Au bump and an Au pad, the thickness of the Au pad is made 0.5 &mgr;m or more and appropriate bonding conditions are adopted as follows: 75 to 300 gf/bump in bonding load; 150 to 250° C. in bonding temperature; and 500 to 800 ms in supersonic wave application time. It is described that 40 to 100 gf/bump can be obtained as the shearing strength for the Au bump bonded portion under the conditions described above. Since the dielectric substrate of the surface wave device is made of a composite oxide system dielectric material, it is described that the device has extremely high strength and suffers from no damage by bonding up to a bonding load of 300 gf/bump. It is described that if the bonding conditions are less than the lower limit values thereof, that is, a bonding load of 75 gf/bump, a bonding temperature of 150° C. and a supersonic wave application time of 300 ms, the bonding strength is lowered and the bonding becomes instable to result in unbonded parts or unbonded bumps thereby lowering the yield or deteriorating the connection reliability, making it difficult to assemble products. Further, only the ceramic substrate is described for the wiring substrate.
On the other hand, a method of mounting a semiconductor chip formed with Au bumps by metal bonding in a face down manner on a wiring substrate containing an organic material is disclosed as the prior art in Japanese Patent Laid-open Hei 10-275826. This prior art describes that a bonded pad portion coated with a hard metal: Ni (3-5 &mgr;m)/Au (0.03-0.05 &mgr;m) on the wiring substrate is cleaned before bonding by irradiation of ions or atoms in vacuum, and a chip used is stored in a non-oxidative atmosphere just after forming the bumps to keep the cleanness and they are bonded to each other. The wiring substrate and the chip are kept for a predetermined period of time in atmospheric air under heating and pressure and an alloy layer is formed between the hard metal and the Au bump to attain metal bonding. The appropriate bonding conditions are defined as 150 to 300° C. in bonding temperature on the side of the chip and 60 to 120° C. on the side of the substrate, 20 to 30 gf/bump in bonding load and 10 to 150 sec in bonding time. Au remains slightly on the surface of the pad after cleaning by the irradiation of ions or atoms and then bonding is conducted under the conditions described above to form an alloy layer between the hard film Ni and Au bump. It is described that they can be bonded so strongly as causing breakage in a state where a portion of the Ni layer is engraved and deposited to the top end of the bump electrode when the bonded portion is put to a rupture test. While it is described that the bonding temperature can be lowered and the bonding time can be shortened by applying supersonic waves, no details are shown.
Upon development of high speed and high function multi-chip modules mounting newest LSI chips, such as microcomputers, image processing devices and memories, we studied and evaluated the existent Au/Au bonding method. It was necessary for the module substrate to have a minimum wiring pitch of 90 to 40 &mgr;m pitch in order to match it with the electrode pitch of the LSI chip. While the usual printed wiring substrate is manufactured by a method of appending a Cu foil and patterning the same by etching, the fine refined pitch is limited to about 100 &mgr;m pitch. In the wiring substrate capable of coping with finer pitches, a build-up substrate formed by successive lamination system of forming a thin insulation film on a core substrate and then forming a pattern by a plating method is most promising in view of productivity, reliability and cost. However, the build-up substrate involves problems that the organic insulation layer formed by successive lamination has a relatively low glass transition temperature (100-150° C.) and low modulus of elasticity and the plating processes is restricted to electroless plating making it difficult to form a thick plating layer in view of cost and that flip chip mounting by the existent Au/Au metal bonding is difficult since the rigidity of fine wiring is low due to the restriction in view of shape and size. Examples of our study made concretely are shown below.
A newest LSI chip was flip-chip mounted by Au/Au bonding on the build-up substrate described above by the supersonic bonding technique described above. As a result, under the conditions of 75 gf/bump in bonding load, 150 to 250° C. in bonding temperature and 300 ms in bonding time, micro-cracks were formed on the insulation layer below Al electrodes of the chip formed with Au bumps and it was found that chip damage gives one of major problems in this mounting method. It was also found that fine wiring was deformed greatly when the build-up substrate was heated by the bonding load and the supersonic vibrations exerted on the fine wiring portion and cracks were formed in the Ni layer plated on the surface thereof to cause wiring disconnection. It was found that when the bonding load was lowered in order to avoid such problems, no sufficient bonding could be obtained and the initial conduction failure due to bonding failure could not be eliminated in the LSI chip of 50 pins or more and it is difficult to attain a bonding ratio of 100%. It was also found that an initial positional displacement of about 20 &mgr;m at the maximum is caused in a chip of 10 mm square at a bonding temperature of 150° C. due to the difference between a heat expansion coefficient of 17 ppm in the organic substrate and a heat expansion coefficient of 3 ppm in the LSI chip, and the positional displacement is promoted in the deformation process of the Au bumps during supersonic bonding tending to cause short circuit failure with respect to adjacent terminals. Further, when bonding was conducted on a pattern with coarse pitches, it was found that while position displacement or short circuit failure was not caused, large thermal strains were caused between the chip and the substrate in the cooling process after bonding to cause chip damage (cracks in the underlying insulation layer) in an LSI with thin Al thickness and weak underlying structure.
On the other hand, in the existent Au/Au bond
Itou Kazutoshi
Kajiwara Ryoichi
Koizumi Masahiro
Morita Toshiaki
Narisawa Akihiko
Dickstein , Shapiro, Morin & Oshinsky, LLP
Prenty Mark V.
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