Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-05-12
2004-12-21
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S270000
Reexamination Certificate
active
06833304
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device in which is formed a MOS FET (Metal-Oxide-Semiconductor Field Effect Transistor) having a trench structure, and a semiconductor device suitably manufactured through the manufacturing method.
2. Description of Related Art
A semiconductor device includes a type provided with a MOS FET (MOS Field Effect Transistor) having a trench structure. In a semiconductor device of this type, a source region and a channel region are placed along the depth direction of the trench, which makes it possible to achieve miniaturization of elements and a reduction of power consumption.
FIG. 3
is a schematic cross section showing a structure of a semiconductor device provided with a MOS FET having the trench structure, obtained through a conventional manufacturing method.
An N
−
epitaxial layer
52
is formed on the surface of a silicon substrate
51
, and a diffusion region
65
is formed on the N
−
epitaxial layer
52
. Trenches
54
, each of which penetrates through the diffusion region
65
and halfway through the N
−
epitaxial layer
52
in the thickness direction, are formed at regular intervals. Inside each trench
54
is provided a gate electrode
55
made of polysilicon, and a gate oxide film
56
is provided to surround the gate electrode
55
.
N
+
source regions
57
and P
+
base regions
58
are formed in the surface layer portion of the diffusion region
65
, and the rest of the diffusion region
65
forms a P
−
channel region
53
. The N
+
source regions
57
are formed on the periphery (rim portion) of each trench
54
. The P
+
base region
58
is formed between every two adjacent N
+
source regions
57
, and is connected to the P
−
channel region
53
.
Insulation films
59
made of silicon oxide are formed to cover above each trench
54
. The insulation films
59
are also present on the periphery of each trench
54
(on the N
+
source regions
57
) when viewed in a plane. A space between every two adjacent insulation films
59
forms a contact hole
60
. An electrode film
61
made of metal, such as aluminum, is formed on the diffusion region
65
and the insulation films
59
. The electrode film
61
is placed to fill in the contact holes
60
.
While the semiconductor device described above is operating, a current flows from the N
+
source regions
57
toward the silicon substrate
51
through the P
−
channel region
53
along the gate oxide films
56
.
FIG.
4
(
a
), FIG.
4
(
b
), and FIG.
4
(
c
) are schematic cross sections used to explain a manufacturing method of the semiconductor device of FIG.
3
.
Initially, the N
−
epitaxial layer
52
is formed on the silicon substrate
51
. Then, impurities used to control a conduction type to be a p-type are introduced into the surface layer portion of the N
−
epitaxial layer
52
, whereby the P
−
channel region
53
is formed. Subsequently, the P
+
base regions
58
and the trenches
54
are formed. Although it does not matter which of the P
+
base regions
58
and the trenches
54
are formed first, the following description will describe a case where the P
+
regions
58
are formed first.
A mask layer
71
having openings (hereinafter, referred to as base-region forming openings)
70
in portions corresponding to the P
+
base regions
58
is formed on the P
−
channel region
53
. Then, impurities are implanted and diffused into the P
−
channel region
53
through the base-region forming openings
70
, whereby the P
+
base regions
58
are formed (FIG.
4
(
a
)). The mask layer
71
is then removed. Subsequently, the N
+
source regions
57
are formed through the same method using another mask layer having openings.
Then, a first resist film
73
having openings (hereinafter, referred to as trench forming openings)
72
in portions corresponding to the trenches
54
is formed on the P
−
channel region
53
. Then, the N
+
source regions
57
, the P
−
channel region
53
, and the upper portion of the N
−
epitaxial layer
52
are etched away through the trench forming openings
72
, whereby the trenches
54
are formed (FIG.
4
(
b
)). The first resist film
73
is then removed, and the inner wall surface of each trench
54
is subjected to thermal oxidation, whereby the gate oxide film
56
is formed.
Then, a polysilicon film is formed to fill in the trenches
54
. Impurities are introduced into the polysilicon film to make the polysilicon film electrically conductive, whereby the gate electrodes
55
are formed. The top surfaces of the respective gate electrodes
55
are flush with the surfaces of the P
+
base regions
58
and the N
+
source regions
57
.
Subsequently, a silicon oxide film
76
is formed across the entire surface of the silicon substrate
51
having undergone the foregoing processes. A second resist film
75
having openings
74
in portions corresponding to the contact holes
60
is then formed on the silicon oxide film
76
(FIG.
4
(
c
)). The silicon oxide film
76
is etched away through the openings
74
of the second resist film
75
, whereby the contact holes
60
are formed. Residual portions of the silicon oxide film
76
form the insulation films
59
. After the second resist film
75
is removed, the electrode film
61
is formed on the silicon substrate
51
having undergone the foregoing processes. The semiconductor device shown in
FIG. 3
is thus obtained.
The base-region forming openings
70
and the trench forming openings
72
are formed through the lithographic technique using a stepper (exposure apparatus). For this reason, the trench forming openings
72
are aligned and formed so that the trenches
54
will be formed at predetermined positions with respect to the P
+
base regions
58
.
Also, the openings
74
used to form the contact holes
60
are aligned and formed so as to avoid portions above the trenches
54
(gate electrodes
55
).
Referring to
FIG. 3
, because the P
+
base regions
58
need to be spaced apart from the gate oxide films
56
, the base-region forming openings
70
are aligned with accuracy within a diffusion margin Md, which is equal to intervals between the P
+
base regions
58
at the predetermined positions and the gate oxide films
56
. Also, because the insulation films
59
need to be present between the respective gate electrodes
55
and the electrode film
61
, the contact holes
60
are aligned with accuracy within a contact margin Mc, which is equal to intervals between the contact holes
60
at adequate positions and the gate electrodes
55
.
Incidentally, in order to meet the demand to reduce power consumption of the power MOS FET, miniaturization of cell pitches has been advancing recently, and the diffusion margin Md and the contact margin Mc are also becoming smaller. On the other hand, according to the manufacturing method as described above, for example, a shift in alignment of approximately 0.3 &mgr;m is inevitably caused during exposure by the exposure apparatus. For these reasons, it has been becoming difficult to form a microscopic MOS FET having a trench structure through the method described above.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a manufacturing method of a semiconductor device, capable of manufacturing a semiconductor device provided with a microscopic MOS FET having a trench structure.
Another object of the invention is to provide a semiconductor device provided with a MOS FET having a trench structure that can be miniaturized.
A manufacturing method of a semiconductor device of the invention is a method of manufacturing a semiconductor device provided with a MOS field effect transistor having a channel region of a first conduction type formed in a surface layer portion of a semiconductor substrate, a source region of a second conduction type formed on a rim
Pham Long
Rabin & Berdo P.C.
Rohm & Co., Ltd.
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