Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-02-08
2003-10-14
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S595000, C438S696000
Reexamination Certificate
active
06632716
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device such as a large-scale integration (LSI) circuit. More specifically, the present invention is directed to a technique capable of stabilizing operation characteristics of such a semiconductor device having an element isolating film on a major surface of a semiconductor substrate.
2. Description of the Conventional Art
SRAMs (static random access memories) are volatile semiconductor devices in which memory cells are arranged at cross points between complementary type data lines (bit lines) and word lines. These data and word lines are arranged in a matrix form.
A memory cell is arranged by a flip-flop circuit and two sets of access transistors. This flip-flop circuit constitutes two storage nodes which are cross-coupled to each other. The storage nodes own bi-stable states of either (High, Low) or (Low, High), and continuously hold the bi-stable states as long as a preselected power source voltage is applied.
In this case, as to the access transistors, one semiconductor region is connected to the storage nodes (input/output terminals of the flip-flop circuit), and the other semiconductor region is connected to the complementary type data line (bit line). The gate electrodes of the access transistors are connected to the word line, and then conductive
on-conductive states of the access transistors are controlled by way of this word line.
When data is written, the word line is selected so as to cause the access transistors to become conductive, and voltage are forcibly applied to a pair of bit lines in response to a desirable logic value, so that the bi-stable state of the flip-flop circuit is set to either (High, Low) or (Low, High).
When data is read, the access transistors are brought into conductive states, and a potential at the storage node is transferred to the bit line. Now, the above-described flip-flop circuit is arranged by two driver transistors and two load elements. As to this driver transistor, a drain region thereof is connected to the semiconductor region of one access transistor, and a source region thereof is connected to a ground line (VEE line). A gate electrode of the driver transistor is connected to the semiconductor region of the other access transistor. Furthermore, one of these load elements is connected to the semiconductor regions of the access transistors, and the other of the load elements is connected to a power source line (VCC line).
Very recently, the following problems are apparently brought up in SRAMs.
First, in order to reduce manufacturing cost by increasing integration degrees of SRAMS, sizes of transistors, in particular, sizes of MOS transistors are necessarily required to be reduced. However, when a gate width of an access transistor is made excessively narrow, a Vth (threshold voltage value) of the access transistor would be increased due to the narrow channel effect, so that reading operation of a memory cell is brought into an unstable condition. Therefore, it is practically difficult that the gate width of the access transistor is shortened up to the region where the Vth increase caused by the narrow channel effect happens to occur. As a consequence, as the gate width of the access transistor, such a narrowest gate width has been employed by which the Vth (threshold voltage value) increase caused by the narrow channel effect can be suppressed, so that the layout area could be reduced.
On the other hand, in order to achieve stable conditions of SRAMs, a cell ratio must be maintained higher than a preselected value (for instance, approximately 3). The cell ratio is defined by a ratio of a current value (driveability) of a driver transistor to a current value (driveability) of an access transistor. However, as previously described, if the current of the access transistor, the gate width of which has been determined, is slightly increased, then this cell ratio would be lowered, resulting in an occurrence of faulty operation.
Now, a first description will be made of the above-described failure operation due to the decrease of the cell ratio.
In general, as is known in the art, the cell operation can be stabilized by increasing a conductance ratio (current ratio) of a driver transistor to an access transistor, so-called as a “cell ratio”, to thereby increase a gain of an inverter, namely to make a sharp inclination of a transition portion of an inverter output. This known idea will now be described based upon an input/output transfer characteristic of one pair of inverters cross-coupled to each other, as indicated in FIG.
31
.
FIG. 32
represents the input/output transfer characteristic of one pair of cross-coupled inverters. In this transfer characteristic, in order to function as a flip-flop, the inverters must own two stable points such as S
1
and S
2
, as represented in FIG.
32
. In order that a memory cell can be practically utilized, it is so designed that regions surrounded by curves shown in
FIG. 32
must be made sufficiently large. As an index, a diameter of a circle indicated in this drawing is sometimes used, which is referred to as an SNM (static noise margin).
Now, a further detailed description will be made of a transfer characteristic of a memory cell of an SRAM as indicated in an equivalent circuit of FIG.
33
.
Normally, since access transistors are under non-conductive states during standby, inverters of the memory cell are constituted by driver transistors and load elements. In this case, since the load elements own high impedances, an inclination of a transition portion of an inverter output becomes sharp as shown in a memory cell transfer characteristic diagram of standby in FIG.
34
. An SNM becomes large. As a result, data can be held under stable condition.
On the other hand, when data is read from the memory cell, the access transistors become conductive, so that a column current flows into a storage node on a Low side. In other words, this is equivalent to such a connection that a load made of the access transistor having the low impedance is connected in parallel to the load element. The inverters of the memory cell must be handled as NMOS type enhancement node inverters constituted by driver transistors and this access transistor as the load. When the cell ratio is low, as indicated in
FIG. 35
, i.e., a memory cell transfer characteristic diagram during data read operation, the gain of the inverter is considerably lowered, as compared with that during standby. Namely, the inclination of the transition portion of the inverter output becomes loose.
Also, a potential at a storage node on a High side is lowered from the power source voltage level during standby up to such a potential value defined by subtracting Vth of the access transistor from the power source voltage, and the SNM is considerably lowered for the time being. At this time, if a sufficiently large SNM is not established, then the bi-stable states will be lost. There is a risk that data may be electrically destroyed.
Under such a reason, normally, the cell ratio is made large in order to avoid the above-explained data destroy. As a result, as illustrated in
FIG. 36
, namely a memory cell transfer characteristic when data is read in case of a large cell ratio, the gain of the inverter becomes large. In other words, the inclination of the transition portion of the inverter output becomes sharp, and the SNM is enlarged.
However, in connection with higher integration of recent semiconductor elements, since layout areas should be reduced, it is practically difficult to widen sizes (gate widths) of driver transistors. As a consequence, in order to stabilize operations of SRAMs, currents of access transistors are required to be reduced.
Referring now to
FIG. 37A
to
FIG. 43
, a description will be made of one modification similar to the conventional semiconductor device manufacturing method as described in IEEE TRANSACTIONS ON ELECTRON DEVICES VOL. 42, No. 7, July 1995, on pages 1303 to 1312.
In this case,
FIG. 37A
to
FIG. 42B
Brock II Paul E
Lee Eddie
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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