Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-18
2002-08-20
Guyka, Alexander G. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S287000, C257S410000, C257S411000
Reexamination Certificate
active
06436777
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the structure of semiconductor devices and manufacturing methods thereof, and particularly to the structure of a gate insulating film of an insulated-gate transistor such as an MOS transistor.
2. Description of the Background Art
<MOS Transistor Structure>
FIG. 30
is a sectional view showing the structure of a conventional MOS transistor. As shown in this diagram, the MOS transistor is fabricated in the transistor formation region between element isolation oxide films
15
,
15
formed in a Si substrate
1
.
That is to say, two source/drain regions
9
are selectively formed in the surface of the transistor formation region of the Si substrate
1
, a gate insulating film
2
is formed on the channel region between the source/drain regions
9
,
9
in the Si substrate
1
, a gate electrode
3
is formed on the gate insulating film
2
, and side walls
16
are formed on the sides of the gate electrode
3
.
The gate electrode
3
is composed of a polysilicon, layer
4
and a silicide layer
11
formed on top of it. Extension regions
8
extend under the side walls
16
from the source/drain regions
9
and silicide regions
10
are formed on the source/drain regions
9
.
The gate insulating film
2
is formed of an oxide film or an oxynitride film or a stacked layer thereof. While the gate electrode
3
is mainly formed of the polysilicon layer
4
in the example of
FIG. 30
, it may be formed by using amorphous silicon as a constituent material.
<Manufacturing Method>
A method for manufacturing the MOS transistor structured as shown in
FIG. 30
is now described.
First, the Si substrate
1
is sectioned with an element isolation structure, such as trench isolation using the element isolation oxide films
15
. Subsequently the entire surface of the Si substrate
1
is thermally oxidized to form the gate insulating film
2
. The polysilicon layer
4
is then laid on the gate insulating film
2
.
Next, an oxide film of TEOS etc. is formed as a hard mask on the polysilicon layer
4
and is patterned by photolithography. Next, the polysilicon layer
4
is anisotropically etched by using the patterned oxide film as a mask (hard mask) to form the gate.
Then an impurity ion implantation is applied by using the gate-shaped polysilicon layer
4
as a mask to form impurity diffusion regions (the extension regions
8
and source/drain regions
9
) and the side walls
16
are formed on the sides of the gate-shaped polysilicon layer
4
. In this process, the impurity diffusion regions under the side walls
16
form the extension regions
8
.
Next, an impurity ion implantation is applied by using the gate-shaped polysilicon layer
4
and the side walls
16
as masks to form the source/drain regions
9
adjoining the extension regions
8
.
Subsequently the oxide film as a hard mask is etched to expose the top surface of the gate-shaped polysilicon layer
4
and then a metal such as cobalt is applied to the entire wafer surface, which is followed by annealing.
Then silicidation occurs in the upper part of the gate-shaped polysilicon layer
4
and in the upper part of the source/drain regions
9
to form the silicide layer
11
and silicide regions
10
. Unreacted metal is removed by wet etching.
The MOS transistor structure shown in
FIG. 30
is thus completed through the above-described processes. Then a semiconductor device containing the MOS transistor is completed through formation of interlayer insulating films not shown in
FIG. 30
, interconnecting process, etc.
For newer generations of semiconductor devices containing MOS transistors as shown in
FIG. 30
, there is an increasing necessity to reduce the power consumption by lowering the power-supply voltage and to enhance the driving current.
That is to say, lowering the power consumption and increasing the speed of semiconductor devices with MOS transistors require lowering the power-supply voltage and increasing the driving current, which have conventionally been realized mainly by reducing the thickness of the SiO
2
gate insulating films (i.e. gate insulating films made of SiO
2
) in the MOS transistors.
FIG. 31
is an explanation diagram showing the off-operation state of the MOS transistor shown in
FIG. 30
, where the MOS transistor is constructed as an NMOS structure. As shown in this diagram, a source terminal
12
is provided on one of the two source/drain regions
9
(silicide regions
10
) and a drain terminal
13
is provided on the other. A gate terminal
14
is provided on the gate electrode
3
and a substrate potential terminal
17
is provided on the Si substrate
1
. The source terminal
12
, gate terminal
14
and substrate potential terminal
17
are set at a potential of 0 V and the drain terminal
13
is set at a potential of 1.5 V.
When the SiO
2
gate insulating film is thinned to a film thickness of 3 nm or smaller, then direct tunneling through the gate insulating film
2
will cause serious gate leakage current I
1
as shown in FIG.
31
. The gate leakage current I
1
may become almost equal to or higher than the leakage current
12
through the normal channel and then it cannot be neglected. That is to say, the standby power (the power in standby state) of the LSI becomes high over the negligible level; the performance of the transistors cannot be further enhanced by thinning the gate insulating films.
As described above, in achieving lower power consumption and higher operation speed of the MOS transistors, the use of SiO
2
as a material of the gate insulating films is reaching a limit and attempts are being made to obtain materials and structures of the gate insulating films which can overcome this problem. In such attempts, high dielectric constant materials having higher dielectric constants than SiO
2
, such as HfO
2
, ZrO
2
, etc., are regarded as likely candidates since these materials are less reactive to the Si substrate in which the MOS transistors are fabricated.
However, it is known that, even when a high dielectric constant material as shown above is used to form the gate insulating film, it reacts with the Si substrate in high temperature processing performed after formation of the gate insulating film and thus forms an oxide film between the Si substrate and itself. The oxide film formed between the Si substrate and the high dielectric constant material reduces the dielectric constant of the gate capacitor structure which has attained large capacitance through the use of the high dielectric constant material. Furthermore, the oxide film obtained by the interface reaction with the Si substrate is uneven rather than flat, which reduces the mobility of carries in the channel formed in the Si substrate under the gate insulating film, thus reducing the driving current.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a semiconductor device which includes an insulated-gate transistor fabricated in a silicon substrate, the transistor comprising a gate insulating film selectively formed on the silicon substrate, the surface of the silicon substrate under the gate insulating film being defined as a channel region, a gate electrode formed of polysilicon on the gate insulating film, and first and second source/drain regions formed in the surface of the silicon substrate with the channel region interposed therebetween, wherein the gate insulating film contains a material having a higher dielectric constant than silicon oxide film and the gate insulating film comprises an upper part, a center part and a lower part, and wherein the lower part is less reactive with the silicon substrate than the center part is and the upper part is less reactive with the gate electrode than the center part is.
Preferably, according to a second aspect, in the semiconductor device, the gate insulating film has first to third high dielectric constant insulating films each having a dielectric constant higher than that of silicon oxide film and the first to third high dielectric constant insulating fi
Guyka Alexander G.
Mitsubishi Denki & Kabushiki Kaisha
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