Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

2000-05-24

2002-08-06

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S275000, C438S522000, C257S355000, C257S357000

Reexamination Certificate

active

06429079

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and their manufacturing method. In particular, the present invention relates to MOS transistors requiring silicide protection and their manufacturing method.
2. Description of the Background Art
In transistors used for logic LSI (large-scale integrated circuit), the reduction in the parasitic resistance of source and drain regions and the wiring resistance of a polysilicon gate electrode at the same time is effected by Salicide (self-aligned silicide) technology in which a silicide film is selectively formed in a self-aligned manner on the surfaces of a source/drain layer and a polysilicon gate electrode.
Silicide films have the advantage of reducing the parasitic resistance and wiring resistance. However, in some cases the presence of a silicide film causes an unfavorable phenomenon. To avoid such a phenomenon, the portion where formation of silicide film is not desirable is protected by a silicide protection film that prevents a silicide film formation.
The problem in forming silicide film and silicide protection film is discussed herebelow. As an example of semiconductor integrated circuits, an inverter circuit C
2
and a protection circuit C
1
protecting it are shown in FIG.
35
.
In the protection circuit C
1
, a P channel MOS transistor P
1
and an N channel MOS transistor N
1
are connected in series and an input pad PD is connected to a node ND
1
connecting the transistors P
1
and N
1
. The gate electrode of the transistor P
1
is connected to a power supply potential (Vcc) and is normally in an OFF state. The gate electrode of the transistor N
1
is connected to a S ground potential and is normally in an OFF state.
In the inverter circuit C
2
, a P channel MOS transistor P
2
and an N channel MOS transistor N
2
are connected in series and a node ND
2
connecting the transistors P
2
and N
2
is connected to another circuit (not shown). The gate electrodes of the transistors P
2
and N
2
are connected to the node ND
1
of the protection circuit C
1
.
If a surge voltage is inputted through the input pad PD, i.e., an ESD (Electro Static Discharge) occurs, a voltage far higher than the operating voltages of normal MOS transistors is applied. Therefore, in the absence of the protection circuit C
1
, the surge voltage will be applied to the gate electrodes of the P channel MOS transistor P
2
and the N channel MOS transistor N
2
in the inverter circuit C
2
so as to possibly cause dielectric breakdown of both the gate insulatings. However, when a surge voltage is applied, the presence of the protection circuit C
1
causes a breakdown between the source and drain of the transistors P
1
and N
1
so that a current flows, which prevents the surge voltage from being applied to the inverter circuit C
2
.
However, when a very large surge voltage is applied between the source and drain in the protection circuit C
1
, the P channel MOS transistor P
1
or the N channel MOS transistor N
1
in the circuit C
1
will be destroyed. A surge voltage that can destroy these channels is called an ESD resistance, and it is desirable to design its value as large as possible. If a silicide film is formed on the surface of the source and drain layer, the ESD resistance might be lowered.
FIG. 36
shows a plane construction of an MOS transistor M
1
. The MOS transistor M
1
comprises a slender gate electrode GE provided in the center, and a source/drain layer SD on its two sides in the shorter direction, and a silicide film SF formed on the surface of the source/drain layer SD.
FIG. 37
is an enlarged view of the area A of FIG.
36
. Generally, the silicide film SF is of polycristal construction and comprises large and small silicide crystal grains GR, as shown in FIG.
37
. Accordingly, each grain shape is reflected in the grain boundaries to exhibit corrugations. This is true for the edge portion of the silicide film SF along with the edge portion of the gate electrode GE. As shown in
FIG. 37
, crystal grains GR face one another across the gate electrode GE. When a surge voltage is applied to such a structure, the surge current is concentrated between the projections (i.e., the space indicated by two arrows in opposite directions) of the crystal grains GR on both sides of the gate electrode GE and, in such portions, the intensive breakage occurs. This makes the MOS transistor inoperative, failing to function as a protection circuit. For this reason, silicide film is not formed on the surface of the source/drain layer in the protection circuit, and a silicide protection film is formed instead.
With reference to
FIG. 38
, the construction of an MOS transistor M
2
with a silicide protection film is described herebelow.
As shown in
FIG. 38
, a silicide protection film SP comprising a silicon oxide film (SiO
2
) is formed on the surfaces of a gate electrode GE and of a source/drain layer SD in the vicinity of the gate electrode GE while no silicide film SF is formed over the silicide protection film SP. This construction allows to increase the distance between the edge of the silicide film SF and the edge of the gate electrode GE. Even if the edge of the silicide film SF is in the shape of a continuous corrugation and hence a surge voltage tends to concentrate on projected portions, the surge current will be dispersed because it must pass a long distance through a lightly doped drain region (not shown) and a source/drain layer. Furthermore, when the surge current passes through the lightly doped drain region having a relatively high resistance, a voltage drop and the like occur and thus prevents the MOS transistor from being damaged.
As described above, the silicide protection film SP has been used to protect a silicide film SF formation in MOS transistors in which its formation can cause disadvantages.
In the formation of a silicide protection film SP, a silicon oxide film is formed over the entire surface of a silicon substrate SB-and the silicon oxide film is then selectively removed by dry etching, such as RIE (Reactive Ion Etching), to form the silicide protection film SP only on the surfaces of a gate electrode GE and of a source/drain layer SD in the vicinity of the gate electrode GE.
Referring to
FIGS. 39 and 40
that are a cross-sectional view of a MOS transistor at a processing step subsequent to the silicide protection film SP formation, the problems resulting from the formation of the silicide protection film are discussed next.
With reference to
FIG. 39
, over an SOI substrate SI, there is a protection region PR in which a plurality of MOS transistors M
1
requiring a silicide protection film will be formed and there is also a normal region OR in which a plurality of MOS transistors M
2
requiring no silicide protection film will be formed. The SOI substrate SI comprises a silicon substrate SB, a buried insulating layer BO, and an SOI layer SL, which are formed in this order on the substrate SB.
In the normal region OR, a silicide film SF is formed over a source/drain layer SD
2
and a gate electrode GE
2
, whereas in the protection region PR a silicide protection film SP of oxide film is formed over the entire surface and there is no silicide film SF over a source/drain layer SDI and a gate electrode GE
1
.
After forming the silicide film SF and the silicide protection film SP, an interlayer insulating film IZ is formed over the SOI substrate SI. Thereafter, as shown in
FIG. 40
, contact holes CH
1
and CH
2
are formed so as to extend through the interlayer insulating film IZ to reach the source/drain layers SD
1
and SD
2
, respectively.
The problem at this time is that the selective ratio of etching differs between the silicide film SF and the silicide protection film SP. That is, since the silicide protection film SP is an oxide film and is more easily etched than the silicide film SF, if the contact holes CH
1
and CH
2
are formed at the same time, the contact hole CH
1
results in somewhat over-etching, or in some cases it extends through the SOI layer to reac

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