Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

1998-06-18

2002-01-29

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S299000, C438S303000, C438S279000

Reexamination Certificate

active

06342421

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof and, more particularly, to a semiconductor device having a shallow, heavily doped source/drain layer, which is formed by applying selective deposition of a silicon layer, and a manufacturing method thereof.
2. Description of the Related Art
In recent years, a large-scaled integrated circuit (LSI) in which a large number of transistors and resistors are coupled to constitute an electric circuit and integrated on one chip is often used in the important portion of a computer or communication equipment.
Selective chemical vapor deposition (selective CVD) has been recently examined as an LSI technology. Selective CVD is applied to, e.g., an elevated source/drain or self-aligned contact technique. With this technique, a silicon layer serving as a source/drain impurity diffused layer or a direct contact layer having excellent characteristics can be formed in one selective growth.
Typical selective CVD for a silicon layer as shown in
FIGS. 1A and 1B
is conventionally known, in which CVD using an Si/Cl/H
2
reduction reactive gas, particularly, dichlorosilane (SiH
2
Cl
2
) source gas added with hydrochloric acid (HCl) gas and H
2
gas is used, and an insulating film
2
such as a silicon oxide film (SiO
2
) and a silicon nitride film (Si
3
N
4
) is used as a mask to selectively grow a silicon layer
3
on the exposed surface of a silicon substrate
1
in the opening portion of the insulating film. Impurity doping into the selectively grown silicon layer
3
is performed by mixing a gasified compound containing impurity atoms with a reactive gas.
In the selective CVD method of this type, however, gas species capable of obtaining a satisfactory selectivity are limited, and the silicon layer
3
is normally epitaxially grown. Therefore, as shown in
FIG. 1B
, a facet
4
having a (
111
) plane is normally formed in the silicon layer
3
.
In addition, when a shallow impurity diffused layer is to be formed, a silicide film is normally formed to decrease the resistance of the impurity diffused layer. More specifically, a titanium film is formed on the impurity diffused layer by sputtering, and annealing is performed by RTA (Rapid Thermal Annealing) at 700° C. for 30 seconds, thereby forming a titanium silicide film.
Since the silicide film is formed upon reaction between a refractory metal film as a silicide film and silicon in the impurity diffused layer, the silicon in the impurity diffused layer is consumed. For this reason, if the depth of the impurity diffused layer is small, the effective thickness of the impurity diffused layer must be increased by selectively growing a silicon layer on the impurity diffused layer.
However, if the silicon layer is obtained as an epitaxially grown film, the facet
4
is formed as in the silicon layer
3
in FIG.
1
B. Therefore, the end portion of the silicon layer becomes thinner to degrade the effect of deposition of the silicon layer.
To avoid this problem, an amorphous silicon layer may be selectively deposited. In this case, however, the deposition temperature or the substrate temperature must be decreased, so as satisfactory deposition rate cannot be ensured.
The conventional direct contact technique has another problem caused by facet formation. This will be described below with reference to the manufacturing steps shown in
FIGS. 2A
to
2
C.
As shown in
FIG. 2A
, BF
2
+
is ion-implanted in the surface of a p-type silicon substrate
11
, thereby selectively forming an n-type impurity diffused region
13
. After an insulating film
12
is deposited on the p-type silicon substrate
11
, an opening portion (contact hole) is formed in this insulating film
12
.
As shown in
FIG. 2B
, a single-crystal silicon layer
14
serving as an electrode containing an impurity is buried in the opening portion by selective epitaxy.
As shown in
FIG. 2C
, a polysilicon layer is deposited on the entire surface and patterned to form a wiring layer
15
.
When this method is used, it becomes difficult to smoothly bury the opening portion because a facet
16
having a (
111
) plane is formed in the single-crystal silicon layer
14
as an epitaxially grown layer.
In addition, to deposit the polysilicon layer serving as the wiring layer
15
, the resultant structure is conveyed from the selective deposition apparatus to the polysilicon layer deposition apparatus while being exposed to air. For this reason, a native oxide film is formed on the upper portion of the single-crystal silicon layer
14
, resulting in an increase in contact resistance with respect to the wiring layer
15
. When the resultant structure is exposed to air, no satisfactory selectivity can be obtained because of a contaminant such as dust, and a short circuit may occur in wiring layer because silicon is deposited on the insulating film
12
in some cases.
Elements become finer as the degree of integration of a semiconductor device is increased. Therefore, when the gate length of a MOS transistor is decreased, the so-called short channel effect such as a decrease in threshold voltage poses a serious problem. To prevent this short channel effect in the MOS transistor, it is conventionally required to decrease the diffusion depth of a source/drain diffused layer. In addition, to maintain a low resistance, it is required to increase the concentration of the source/drain layer.
These requirements are particularly needed at the end portion of a source/drain diffused layer. More specifically, as the elements become finer, it becomes more preferable that the end portion of the source/drain layer have a high concentration and a small diffusion depth. To cope with these requirements, an LDD (Lightly Doped Drain) structure is conventionally adopted as a source/drain diffusion layer structure.
The LDD structure is obtained by the following method. After a gate electrode is formed, ion implantation is performed at a low acceleration voltage and a low dose to form a shallow, lightly doped source/drain layer. Subsequently, a side-wall gate oxide film is formed. Thereafter, ion implantation is performed at a high acceleration voltage and a high dose to form a deep, heavily doped source/drain diffused layer. To further decrease the resistance, a silicide film is normally formed on the source/drain diffused layer.
To make the elements finer by using the LDD structure, the acceleration voltage of ion implantation of the impurity into the gate electrode end portion must be decreased, or the dose amount must be decreased.
However, when the acceleration voltage of ion implantation is decreased to form a shallow, lightly doped source/drain layer, the beam current in ion implantation decreases, resulting in a degradation in throughput.
When the acceleration voltage is low, the influence of channeling in the profile of ion implantation becomes conspicous, so no shallow diffused layer can be formed even by decreasing the acceleration voltage. When the acceleration voltage is lower, the surface of the substrate is undesirably sputtered.
As described above, ion implantation has a limit in formation of shallow junction in principle. More specifically, the distribution of the implanted impurity largely depends on the acceleration energy in ion implantation. To obtain a shallow junction, a shallow ion implantation distribution must be obtained.
The implantation depth is almost inversely proportional to the mass of ions. For this reason, in formation of a p
+
-layer, for which no appropriate impurity is present except for boron, it becomes more difficult to obtain a shallow ion implantation distribution. Conventionally, to effectively decrease the acceleration energy, BF
2
+
ions are used.
In this method, a source/drain layer is formed by known ion implantation. More specifically, a silicon oxide film and a polysilicon film are sequentially formed on an element region isolated by an element isolation insulating film formed on a silicon substrate. A resist pattern is

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