Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-01-04
2011-01-04
Richards, N Drew (Department: 2895)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S195000, C438S241000
Reexamination Certificate
active
07863131
ABSTRACT:
Semiconductor device and manufacturing method for reducing the number of required lithography masks added to the nonvolatile memory in the standard CMOS process to shorten the production period and reduce costs. In a split-gate memory cell with silicided gate electrodes utilizing a sidewall structure, a separate auxiliary pattern is formed adjoining the selected gate electrodes. A contact is set on a wiring layer self-aligned by filling side-wall gates of polysilicon in the gap between the electrodes and auxiliary pattern. The contact may overlap onto the auxiliary pattern and device isolation region, in an optimal design considering the size of the occupied surface area. If the distance to the selected gate electrode is x, the ONO film deposit thickness is t, and the polysilicon film deposit thickness is d, then the auxiliary pattern may be separated just by a distance x such that x<2×(t+d).
REFERENCES:
patent: 6528390 (2003-03-01), Komori et al.
patent: 2004/0065917 (2004-04-01), Fan et al.
patent: 2004/0085802 (2004-05-01), Yang et al.
patent: 2004/0119107 (2004-06-01), Hisamoto et al.
patent: 2004/0185628 (2004-09-01), Choi
patent: 2005/0205922 (2005-09-01), Liu et al.
patent: 2005/0207199 (2005-09-01), Chen et al.
patent: 05-048113 (1991-08-01), None
patent: 05-121700 (1991-08-01), None
patent: 2001-326286 (2000-05-01), None
patent: 2004-186452 (2002-12-01), None
Kianian et al., “A Novel 3 Volts-Only, Small Sector Erase, High Density Flash E2PROM”, Symposium on VLSI Technology Digest of Technical Papers, (1994) IEEE, pp. 71-72.
Chen et al., “A Novel Flash Memory Device with S Plit Gate Source Side Injection and ONO Charge Storage Stack (SPIN)”, Symposium on VLSI Technology Digest of Technical Papers, (1997), pp. 63-64.
Tanaka et al., “A 512kb MONOS Type Flash Memory Module Embedded in a Microcontroller”, Symposium on VLSI Circuits Digest of Technical Papers, (2003).
Hisamoto Digh
Ishimaru Tetsuya
Yasui Kan
A. Marquez, Esq. Juan Carlos
Lee Jae
Renesas Electronics Corporation
Richards N Drew
Stites & Harbison PLLC
LandOfFree
Semiconductor device and manufacturing method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and manufacturing method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and manufacturing method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2624412