Semiconductor device and its manufacturing method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S272000, C438S589000

Reexamination Certificate

active

06858500

ABSTRACT:
Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

REFERENCES:
patent: 5250450 (1993-10-01), Lee et al.
patent: 5701026 (1997-12-01), Fujishima et al.
patent: 5828100 (1998-10-01), Tamba et al.
patent: 5903034 (1999-05-01), Sakamoto et al.
patent: 6316807 (2001-11-01), Fujishima et al.
patent: 6359318 (2002-03-01), Yamamoto et al.
patent: 6495883 (2002-12-01), Shibata et al.
patent: 6545316 (2003-04-01), Baliga
patent: 6624470 (2003-09-01), Fujishima
patent: 6639274 (2003-10-01), Fujishima
patent: 6664163 (2003-12-01), Fujishima et al.
patent: 6781197 (2004-08-01), Fujishima et al.
patent: 197 20 193 (1998-11-01), None
patent: 102 11 690 (2002-09-01), None
patent: 6-104446 (1994-04-01), None
patent: 8-088283 (1996-04-01), None
patent: 2000-77532 (2000-03-01), None
patent: 2002-184980 (2002-06-01), None
patent: WO 0052760 (2000-09-01), None
patent: WO 0141187 (2001-06-01), None
N. Fujishima, et al., A Low On-resistance Trench Lateral Power MOSFET in a 0.6 μm Smart Power Technology for 20-30 V Applications, Dec. 8, 2002, pp. 455-458.
M.S. Shekar, et al., Hot Electron Degradation and Unclamped Inductive Switching in Submicron 60-V Lateral DMOS, Mar. 31, 1998, pp. 383-390.
Naoto Fujishima et al., “A High Density, Low On-resistance, Trench Lateral Power MOSFTET with a Trench Bottom Source Contact”, ISPSD Proceedings 2001, pp143-146.
U.S. Appl. No. 10/156,641, filed May 29, 2002, Naoto Fujishima, Fuji Electric Co., Ltd.
U.S. Appl. No. 10/156,757, filed May 29, 2002, Naoto Fujishima, Fuji Electric Co., Ltd.
U.S. Appl. No. 10/103,543, filed Mar. 21, 2002.
U.S. Appl. No. 10/272,304, filed Oct. 17, 2002, Naoto Fujishima et al., Fuji Electric Co., Ltd.
U.S. Appl. No. 10/322,367, filed Dec. 18, 2002, Tabuchi et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor device and its manufacturing method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device and its manufacturing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and its manufacturing method will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3489500

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.