Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-09-12
2004-02-17
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S296000, C257S303000, C257S304000, C257S306000, C438S691000, C438S692000
Reexamination Certificate
active
06693002
ABSTRACT:
This application is based on Japanese Patent Application 2000-104361, filed on Apr. 6, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture, and more particularly to a semiconductor device having capacitors and a semiconductor device manufacture method.
b) Description of the Related Art
A dynamic random access memory (hereinafter called “DRAM”) is generally constituted of one transistor and one capacitor per one memory cell. In order to increase a memory capacity, it is necessary to form memory cells as many as possible in a limited memory cell array area.
In a DRAM memory cell array, word lines also used as gate electrodes of memory cell transistors and bit lines for charging and discharging capacitors are disposed crossing each other.
Each capacitor is constituted of a storage electrode connected to a transistor, a capacitor dielectric film and a cell plate electrode opposing the storage electrode.
As a technique of improving the integration degree of DRAM, a capacitor over bit line structure is known in which after word lines and bit lines are formed on a semiconductor substrate, capacitors are formed over these lines. The capacitor storage electrode is required to be connected to one of drain and source regions of a memory cell transistor. In order to reliably form a contact hole through an insulating film, a self aligned contact (hereinafter called SAC) structure has been adopted.
With this SAC structure, the upper surface and side walls of a word line of a memory cell transistor are covered with, for example, a silicon nitride film. Since the silicon nitride film functions as an etch stopper while a contact hole is formed through an insulating film, even if the position of the contact hole is displaced to some extent, the source/drain region can be exposed reliably. During this etching, the word line also functioning as the gate electrode can be insulated and electrically protected by the silicon nitride film.
The SAC structure is also applied to the case wherein after the word line is buried in the insulating film, a bit line is formed on the surface of the insulating film. The upper surface and side walls of the bit line are covered with a silicon nitride film so that a contact hole can be formed reliably exposing a contact area while the bit line is insulated and electrically protected by the silicon nitride film.
Further improvement on the integration degree of DRAM and further reduction of the manufacture cost of DRAM are desired. In order to reliably manufacture a high integration DRAM, it is desired to simplify the manufacture processes.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide manufacture processes for semiconductor devices of high integration, low cost and high reliability.
It is another object of the present invention to provide semiconductor devices of high integration, low cost and high reliability.
According to one aspect of the present invention, there is provided a capacitor comprising: a substrate having a first area and a second area surrounding said first area; an insulating film formed in said second area; an electrode formed above a surface of said substrate in said first area; a dielectric film formed on said electrode; and an opposing electrode formed on said dielectric film, wherein a shape of a side wall of said insulating film includes a shape reflecting an outer peripheral shape of a side wall of said electrode facing the side wall of said insulating film.
According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having a first area and a second area surrounding said first area; a first insulating film formed above said semiconductor substrate; a contact hole formed through said first insulating film in said first area; a second insulating film formed above said first insulating film in said second area; an electrode electrically connected to said semiconductor substrate via said contact hole; a dielectric film formed on said electrodes; and an opposing electrode formed on said dielectric film, wherein a shape of a side wall of said second insulating film includes a shape reflecting an outer peripheral shape of a side wall of said electrode facing the side wall of said second insulating film.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: (a) forming a first insulating film above a semiconductor substrate having a first area and a second area surrounding said first area;(b) forming a first contact hole through said first insulating film in said first area, said first contact hole reaching said semiconductor substrate;(c) forming a second insulating film above said first insulating film;(d) forming a second contact hole through said second insulating film in said first area, said second contact hole reaching said first contact hole;(e) forming an electrode electrically connected to said semiconductor substrate in said second contact hole;(f) performing an etching process to expose a side wall of the electrode and reflect an outer peripheral shape of the side wall of said electrode upon an outer peripheral shape of a side wall of said second insulating film left in said second area surrounding said first area;(g) forming a dielectric film covering an exposed surface of said electrode; and (h) forming an opposing electrode on said dielectric films.
As above, the storage electrode having a bath tub shape can be formed without using a mask. The number of manufacture processes for semiconductor devices such as DRAM can be reduced. The manufacture cost of semiconductor devices can be reduced greatly.
In DRAM manufacture processes, the boundary between the memory cell area and peripheral circuit area can be defined in a self alignment manner without using a mask. It is unnecessary to consider an alignment margin. An additional area for providing a margin of the boundary between the memory cell area and peripheral circuit area is not necessary so that the integration degree of semiconductor integrated circuits can be improved. The boundary area between the memory cell area and peripheral circuit area can be reduced to a minimum necessary area. Since an additional area is not necessary, the integration degree can be improved.
REFERENCES:
patent: 6258649 (2001-07-01), Nakamura et al.
patent: 6323100 (2001-11-01), Kimura
patent: 6501119 (2002-12-01), Ohno
patent: 08-330539 (1996-12-01), None
patent: 10-284700 (1998-10-01), None
patent: 11-017144 (1999-01-01), None
Fukuzumi Yoshiaki
Hatada Akiyoshi
Nakamura Shunji
Fujitsu Limited Kabushiki Kaisha Toshiba
Nelms David
Tran Mai-Huong
Westerman Hattori Daniels & Adrian LLP
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