Semiconductor device and its manufacture

Details Semiconductor device and its manufacture Semiconductor device and its manufacture

2000-05-16

2004-02-10

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S306000, C257S330000

Reexamination Certificate

active

06690050

ABSTRACT:

This application is based on Japanese Patent Application HEI 11-136658 and 2000-109796, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to the structure of a semiconductor device having both dynamic random access memories (DRAM) and logic circuits on the same substrate.
b) Description of the Related Art
FIGS.
29
(A) to
38
are diagrams illustrating a conventional method of manufacturing a semiconductor device with DRAM and logic circuits.
In each figure, the right side shows a CMOS transistor area in a logic area, and the left side shows a DRAM memory area.
First, as shown in FIG.
29
(A), element isolation regions
102
are formed on a silicon substrate
101
by well-known element isolation techniques such as shallow trench isolation (STI) techniques to separate active regions.
If necessary, n-wells are formed in a p-channel transistor area and p-wells are formed in an n-channel transistor area and a memory cell area. A channel stop layer for preventing leak current between element forming regions and a channel dope layer for controlling Vth are also formed. Three masks (resist patterns) in total are required to form a p-well and an n-well in the logic area and a p-well in the memory cell area by using different ion implantation. If a triple well is to be formed, four masks in total are required.
Next, as shown in FIG.
29
(B), a gate oxide film Gox is formed on the active region through thermal oxidation, and an amorphous silicon layer
103
is formed on the gate oxide film Gox. A resist pattern
104
exposing the n-channel transistor area and memory cell area is formed on the amorphous silicon layer
103
. Arsenic or phosphorous ions are implanted to change the n-channel transistor area and memory cell area of the amorphous silicon layer
103
to an n-type amorphous silicon layer
103
a.
In the following drawings, the gate oxide film Gox is omitted.
As shown in FIG.
30
(A), after the resist pattern
104
is removed, a resist pattern
105
exposing the p-channel transistor area is newly deposited. Boron or boron fluoride ions are implanted to change the amorphous silicon layer
103
on the p-channel region to a p-type amorphous silicon layer
103
b.
By implanting n-type impurities into the silicon layer to be used as the gate in the n-channel transistor area and p-type impurities into the silicon layer to be used as the gate in the p-channel transistor area, as described above, resistance against the short channel effects can be made high because surface channel type transistors can be formed by utilizing a work function difference. This structure requires two masks (resist patterns).
As shown in FIG.
30
(B), after the resist pattern
105
is removed, a tungsten silicide (WSi) layer
106
and a silicon nitride film
107
are sequentially deposited by chemical vapor deposition (CVD), and patterned into a gate electrode shape by well-known photolithography techniques. The gate electrode in the memory cell area also functions as a word line.
As shown in FIG.
31
(A), a resist pattern
108
exposing the p-channel transistor area is formed. Boron ions are implanted into the substrate to form a lightly doped drain (LDD) regions (p
−
type impurity diffusion layer)
109
of a p-channel transistor.
As shown in FIG.
31
(B), after the resist pattern
108
is removed, a resist pattern
110
is formed to expose the n-channel transistor area in the logic area. Phosphorous ions are implanted into the substrate to form a low concentration regions (LDD regions, n-type impurity diffusion regions)
111
of an n-channel transistor.
As shown in FIG.
32
(A), after the resist pattern
110
is removed, a resist pattern
112
is formed to expose the memory cell area. Phosphorous ions are implanted into the substrate to form an n-type impurity diffusion regions (source/drain regions)
113
of a transistor in the memory cell area.
Next, as shown in FIG.
32
(B), after the resist pattern
112
is removed and a silicon nitride film
114
is formed, the memory cell area is covered with a resist pattern
115
to anisotropically and selectively etch the nitride film in the CMOS area. The nitride film on the flat surface is removed to form side wall spacers
114
a
on the side walls of the gate electrodes of n- and p-channel transistors in the CMOS area.
In this case, the source/drain regions in the memory cell area are being covered with the silicon nitride film.
Next, similar to the processes shown in FIGS.
31
(A) and
31
(B), by using different resist patterns, boron ions are implanted into the p-channel transistor area to a high concentration and arsenic ions are implanted into the n-channel transistor area to a high concentration to form source/drain regions (p
+
-type impurity diffusion regions
116
and n
+
-type impurity diffusion regions
117
), as shown in FIG.
33
. Thereafter, the resist pattern used as the mask is removed.
Next, a cobalt (Co) film is formed on the surface of the semiconductor substrate by sputtering, and heat treatment is performed to react Co with the exposed silicon surface. Then, unreacted cobalt film is removed. With these processes, a cobalt silicide layer
118
is formed on the source/drain regions
116
and
117
in the CMOS area. A process of forming the silicide layer through reaction between exposed silicon and cobalt and removing the unreacted metal layer to from the silicide layer only on the silicon area is called a salicide (self-aligned silicide) process.
As shown in
FIG. 34
, after a BPSG layer
119
is formed by CVD, the surface of this layer is planarized by a chemical mechanical polishing (CMP) method or the like. Next, contact holes
120
are formed through the BPSG layer
119
in the areas corresponding to the source/drain regions
113
by well-known photolithography techniques. In this case, BPSG is etched under the conditions that the nitride film is hard to be etched, and the exposed nitride film is anisotropically etched to expose the surfaces of the source/drain regions
113
in the memory cell area.
The contact holes
120
can be formed in self-alignment with the side wall spacers
114
b
because these spacers of nitride are formed on the side walls of the gate electrode to be used also as the word line. A process of forming a contact hole by utilizing an insulating film on the side walls of a wiring layer is generally called a SAC (self-aligned contact) method.
As shown in
FIG. 35
, a silicon film is formed on the BPSG layer
119
, filling the contact holes
120
. Thereafter, the surface of the semiconductor substrate is planarized to remove the silicon film in the area other than the contact holes and leave the silicon layer only in the contact holes
120
, so that silicon plugs
121
can be formed. Next, another BPSG layer
122
is formed and by using a resist pattern, a contact hole is formed through the BPSG layer
122
in the area corresponding to the silicon plug
121
to be connected to a bit line. A bit line
123
of tungsten or the like is formed and connected to the silicon plug
121
via the contact hole.
As shown in
FIG. 36
, a BPSG layer
124
is formed and the surface thereof is planarized. Contact holes for a storage electrode are formed through the BPSG layer
124
in areas corresponding to the silicon plugs
121
on both sides of the plug
121
connected to the bit line. Then, a storage electrode
125
, a capacitor dielectric film
130
and an opposing electrode
126
are formed.
As shown in
FIG. 37
, after a BPSG layer
127
is formed over the capacitor, contact holes for the source/drain regions
116
and
117
in the CMOS area are formed through the BPSG layer
127
. Al wiring layers
128
are formed on the BPSG layer
127
, the Al wiring layers
128
being connected via the contact holes to the source/drain regions
116
and
117
in the CMOS area.
Thereafter, a passivation film is formed, bonding openings are formed and ot

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