Semiconductor device and fabrication method thereof

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads

Reexamination Certificate

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Details

C257S750000, C257S780000, C257SE23021, C257SE21508, C438S612000, C438S613000

Reexamination Certificate

active

07489037

ABSTRACT:
A semiconductor device and a fabrication method thereof are proposed. A first dielectric layer is formed on a semiconductor substrate having at least one bond pad, wherein the first dielectric layer has a first opening for exposing the bond pad and a second opening at a predetermined position for redistribution. A first metallic layer is applied on the first dielectric layer and in the first and second openings. A second metallic layer and a third metallic layer are formed on the first metallic layer at positions corresponding to the first and second openings, respectively. A second dielectric layer and a solder bump are formed on the second and third metallic layers, respectively. The second metallic layer can assure electrical quality of the first metallic layer corresponding to the first opening without having an electrical break of the first metallic layer for redistribution.

REFERENCES:
patent: 6656826 (2003-12-01), Ishimaru
patent: 7091121 (2006-08-01), Horng
patent: 7223683 (2007-05-01), Lin
patent: 2003/0153172 (2003-08-01), Yajima et al.
patent: 2004/0266163 (2004-12-01), Horng
patent: 2006/0019480 (2006-01-01), Cheng et al.
patent: 2006/0073693 (2006-04-01), Huang
patent: 543125 (1991-05-01), None

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