Semiconductor device and fabrication method thereof

Details Semiconductor device and fabrication method thereof Semiconductor device and fabrication method thereof

2000-09-28

2002-11-05

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S266000, C438S294000, C438S545000, C257S355000

Reexamination Certificate

active

06475861

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor, and more particularly to an improved semiconductor device and fabrication method thereof for forming a guard ring between n-wells provided for fabricating a peripheral circuitry adjacent to an input protection transistor, thereby stabilizing a current-voltage operation characteristic of an input pad.
2. Description of the Background Art
Among semiconductor devices, a DRAM (Dynamic Random Access Memory) refers to a memory device wherein a basic cell is provided with a selection transistor and a capacitor. A gate of the selection transistor is connected to a word line, a drain thereof is connected to a bit line, and a source thereof is connected to an electrode or the capacitor, that is, to an earthed electrode. Such a DRAM stores therein data depending upon whether there is an electrical charge loaded in the capacitor. The DRAM developed in the 1970's is still being studied for its larger integration.
FIG. 1
is a cross-sectional view illustrating a semiconductor device with regard to an input pad peripheral circuit according to a background art. As shown therein, a plurality of device isolation regions a, b, c are formed in the upper surface of a semiconductor substrate
10
. A first and second n-wells
20
,
30
are formed adjacent to the device isolation regions a, b in the semiconductor substrate
10
. The first and second n-wells
20
,
30
are isolated by the device isolation region b. In the first n-well
20
there is formed an n+ diffusion layer
21
which is connected to a first supply voltage Vdd. In the second n-well
30
there are formed an p+ diffusion layer
31
which is connected to first supply voltage Vdd, and a p+ diffusion layer
32
which is connected to a second supply voltage Vcc. A p-channel transistor Q
2
having the p+ diffusion layers
31
,
32
as drain and source and having a gate electrode G
2
is formed in the second n-well
30
. The first supply voltage Vdd denotes an internal supply voltage generated from an externally applied supply voltage Vcc and is generally lower than the externally applied supply voltage Vcc. To the left side from the first n-well
20
, there is provided an input protection transistor Q
1
adjacent to the device isolation region a. The input protection transistor Q
1
is an n-channel transistor. The n-channel transistor Q
1
includes the gate electrode G
1
formed in the upper surface of the semiconductor substrate
10
, and the n+ diffusion layers
11
,
12
as source and drain, respectively. The gate electrode of the input protection transistor Q
1
and the n+ diffusion layer
12
are connected to a ground voltage Vss serving as a third supply voltage. The n+ diffusion layer
11
is connected to an input voltage Vin which is received from an input pad (not shown). An n+ diffusion layer
13
is horizontally spaced from the left side of the input protection transistor Q
1
and adjacent to the device isolation region c, and it is connected to the third supply voltage. A horizontal npn parasite bipolar transistor Q
3
is formed by the n+ diffusion layer
11
connected to the input voltage Vin of the input protection transistor Q
1
and by the n+ diffusion layer
13
connected to the third supply voltage Vss.
Voltage V
GD
connected to the gate electrode G
2
of the p-channel transistor Q
2
denotes a voltage applied to the gate of the p-channel transistor Q
2
and a voltage of 0V is applied thereto. Here, voltage V
BB
denotes a back bias voltage.
In the input pad peripheral circuitry as shown in
FIG. 1
, when the input voltage Vin is less than a threshold voltage Vth, the input protection transistor Q
1
5
is turned on, thereby allowing current to flow to an input voltage Vin of the input protection transistor Q
1
.
Here, when a temperature goes up, electron-hole pairs are generated from a depletion region provided between the first n-well
20
and the p-type semiconductor substrate
10
, whereby holes h+ flow toward the p-type semiconductor substrate
10
, and electrons e− flow toward the first n-well
20
.
At this time, the first n-well is in a floating state so that the received electrons e− serve to lower the voltage, whereby a forward voltage is applied between the first n-well
20
and the p-type semiconductor substrate
10
. Accordingly, electrons are injected toward the p-type semiconductor substrate
10
.
When electrons are injected into the p-type semiconductor substrate
10
, the injected electrons are turned to a base current of parasite bipolar transistor Q
3
, and the current amplified as much as the gate of the transistor is applied between n+ region
11
to which is applied Vin and n+ region
13
which is connected to Vss.
As a result, when the first n-well
20
and the second n-well
30
are biased by Vdd and an open/short test is carried out, a stable current-voltage characteristic is not realized around the input pad peripheral circuitry.
That is, the input pad peripheral circuitry of the conventional DRAM device according to the conventional art has several disadvantages: firstly, because the input protection transistor Q
1
is activated by a thermal carrier generated in a high temperature, there is a strong possibility of incurring an operational error in the DRAM device; and secondly, when carrying out an open/short test by biasing the n-well regions
20
,
30
to the first supply voltage Vdd, the n-well regions respectively remain in a floating state, thereby incurring a device error in a high possibility.
SUMMARY OF THE INVENTION
The present invention is devised to solve the above-described problem. Accordingly, it is an object of the present invention to provide a semiconductor device and fabrication method thereof which makes it possible to realize a stabilized current-voltage characteristic during an open/short test in an input pad peripheral circuitry by forming a guard ring between an input protection transistor and a first n-well adjacent to the transistor.
To achieve the above-described object, there is provided a semiconductor device according to the present invention which includes a semiconductor substrate having a plurality of device isolation regions, first and second n-wells horizontally spaced from either of the plurality of device isolation regions, a p-channel transistor formed in the second n-well, an input protection transistor horizontally spaced from the first n-well and the device isolation region, on a symmetrical portion by the first n-well to the second n-well, and a guard ring formed between the first n-well and the input protection transistor.
Further, to achieve the above-described object, there is provided a semiconductor device fabrication method according to the present invention which includes the steps of preparing a semiconductor substrate having a device isolation region, forming a first mask pattern on a surface portion of the semiconductor substrate which is not to include first and second n-wells, implanting n-type impurities into the semiconductor substrate to form the first and second n-wells, removing the first mask pattern, forming a first gate electrode over a surface portion of the semiconductor substrate which does not include any of n-wells, and a second gate electrode over the second n-well, forming a second mask pattern on the second n-well and the second gate electrode, implanting n+ impurities into each side portion from the grist gate electrode and the first n-well which are not covered with the second mask pattern to form an n+ diffusion layer, removing the second mask pattern, forming a p+ diffusion layer on each side portion from the second gate electrode in the second n-well, and forming a guard ring along an interface between the semiconductor substrate and the first n-well.
Still further, to achieve the above-described object, there is provided a semiconductor device fabrication method according to the present invention which includes the steps of

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