Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-11-02
2002-11-26
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S614000, C438S656000, C438S687000
Reexamination Certificate
active
06486053
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device and a fabricating method therefor which result in a reduction in time and cost for the fabricating processes and also achieve reliability in a phased layer of under bump metallurgy (hereinafter referred to as UBM).
2. Description of the Prior Art
In general, demands for high speed, high density and multi-function in electronic devices have been satisfied by advanced fabricating techniques for narrow width through reduction in the dimension of semiconductor chips and progress in integration of single elements. Accordingly, there has been a reduction in step pitch between pads of the semiconductor chip. As the step pitch has recently decreased to less than 50 microns, there is a difficulty in making electrical connections between pads using conventional wire bonding equipment. In addition, as the number of single elements per unit area increases, so do power consumption and processing delay in the semiconductor device.
In order to solve the aforementioned problems, a flip chip attachment technique has been introduced. According to the flip chip attachment technique, the conventional pad structure is modified into a new pad structure. Specifically, an opening is formed to expose a portion of a passivation layer deposited on final metal circuitry of the conventional pad structure, so that the pad is bonded with gold wire. In the flip chip attachment technique, in addition to all the conventional steps for forming the opening to expose a pad at a portion of the passivation layer deposited on the final metal circuitry, an E-beam evaporation is performed to deposit metal for UBM and solder bump, and the solder is reflowed in an atmosphere of hydrogen to modify the metal into a ball. In the course of the E-beam evaporation, masking with Mo is used such that the metal is selectively deposited for the UBM and solder.
However, there are at least two problems with such a flip chip attachment technique. The first problem is high cost for fabricating processes. That is, while selective deposition is performed with a mask of Mo, the thickness of the metal deposited for UBM is less than 1 micron, but the deposition thickness for the solder is greater than 70 microns. Therefore, there may be a great loss of deposition material in the process of the E-beam evaporation with low throughput. Furthermore, the second problem is a difficulty in controlling the resolving power of the Mo mask for reduction in the dimension of the semiconductor device. That is, in the case in which the selective deposition is performed with a Mo mask, there is no specific difficulty in forming a pattern for a pad at the mask because the dimension of the bump is greater than 100 microns according to a design rule for fabricating the bump of 0.25 micron. However, as the dimension of the bump for semiconductor devices reduces to 75 microns, there is difficulty in forming a pattern for a pad at the mask. In addition, the mask can cause a mismatch in the process of loading a wafer onto the E-beam evaporation equipment, thereby resulting in errors in the resulting pattern.
In order to solve the aforementioned problem in the E-beam evaporation, there has been introduced a method of depositing UBM over the substrate and selectively electroplating solder.
FIGS. 1 through 6
are schematic cross-sectional diagrams which illustrate the formation of a device using this process. As shown in
FIG. 1
, in accordance with this prior art fabrication method, a substrate
10
is prepared with an aluminum electrode pad
11
disposed thereon. A passivation layer
13
of oxide or nitride film is deposited along with the pad
11
. An opening is formed in the passivation layer
13
to expose the pad
11
. A polyimide layer (not shown) having another opening, larger than and overlapping that of the passivation layer, can optionally be additionally formed on the passivation layer
13
to relieve stress onto a lower layer of UBM, that is, a chrome layer
21
, which is formed during subsequent process steps.
Then, as shown in
FIG. 2
, in order to form the UBM
20
, a lower metal layer
21
of chrome and an intermediate layer including a phased layer
23
and an upper metal layer
25
of copper are deposited in sequence. Then, as shown in
FIG. 3
, a photoresist layer
30
is coated on the UBM
20
to prevent etching and is patterned by a lithography technique to form an opening, identical or larger than that formed on the pad
11
. Then, as shown in
FIG. 4
, the structure is electroplated with solder, and the photoresist layer
30
is removed to form a pole-type solder layer
40
. The solder layer
40
can also be formed in the shape of a mushroom. Then, as shown in
FIG. 5
, the solder layer
40
is used as a mask to etch out the surrounding UBM
20
to expose the passivation layer
13
. Finally, as shown in
FIG. 6
, the solder layer
40
is transformed into a solder ball
41
for a bump through a conventional re-flow process.
FIG. 7
is a graph which illustrates a composition profile in the UBM manufactureed by this process. As shown in the graph of
FIG. 7
, by depositing less chrome and more copper in the prior art, a reliable phased layer
23
with a favorable Auger profile (AES Profile) has been made. That is, as shown with a solid line in
FIG. 7
, the composition ratio of chrome is constant at 100% in the chrome layer
21
. It gradually decreases in the phased layer
23
toward the copper layer
25
and becomes constant at 0% in the copper layer
25
. As shown with a dotted line in
FIG. 7
, the composition ratio of copper is constant at 0% in the layer
21
. It gradually increases in the phased layer
23
toward the copper layer
25
and becomes constant at 100% in the copper layer
25
.
There is a problem in this prior art approach in that the E-beam evaporation process is performed to make the phased layer
23
. This slows down the process of depositing the UBM
20
, resulting in increase in operational time and cost.
In order to solve this problem in the prior art, sputtering equipment has been modified to make the phased layer of UBM. Such modified sputtering equipment is made in a double target system having internal and external targets. However, the modified sputtering equipment may bring about poor uniformity in thickness of the phased layer over the wafer and poor composition ratio between chrome and copper in the phased layer, thereby reducing reliability of the phased layer.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to solve the aforementioned problems and provide a semiconductor device and a device processing method to ensure a desired thickness of the phased layer of UBM to achieve reliability in uniformity.
It is another object of the present invention to provide a semiconductor device and a device processing method to increase speed in deposition of UBM and reduce cost in fabricating processes.
In accordance with the invention, there is provided a semiconductor device and a method of fabricating a semiconductor device which achieve these objects. The device of the invention includes a semiconductor substrate having a conductive electrode pad. Under bump metallurgy (UBM) is formed on the electrode pad with a first metal layer, a third metal layer and a phased layer therebetween. The phased layer includes second and fourth metal layers made of the same material as the first and third metal layers, respectively, for sequential deposition. The second metal layer gradually gets thinner from the first metal layer toward the third metal layer, and the fourth metal layer gradually gets thicker from the first metal layer toward the third metal layer. A conductive bump is formed on the UBM.
The second and fourth metal layers may be made of the same, thin multi-layers possible for mutual diffusion. Alternatively, they can be made of a mono-layer.
In one embodiment, the first and second metal layers are made of chrome, and the third and four
Kim Byung-Soo
Lee Chang-Hun
Lee Soo-Cheol
Yi Sang-Don
Mills & Onello LLP
Quach T. N.
Samsung Electronics Co,. Ltd.
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