Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-07-19
2011-07-19
Wojciechowicz, Edward (Department: 2895)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S289000, C438S306000, C438S524000, C438S529000, C438S530000
Reexamination Certificate
active
07981747
ABSTRACT:
A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p−type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p−type semiconductor region is formed under a n+type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.
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Nakazawa Yoshito
Shiraishi Masaki
Marquez, Esq Juan Carlos A.
Renesas Electronics Corporation
Stites & Harbison PLLC
Wojciechowicz Edward
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