Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-09-11
2001-03-27
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S629000
Reexamination Certificate
active
06207486
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a method for manufacturing semiconductor devices and forming a wiring layer. More particularly, but not exclusively, the invention relates to a semiconductor device manufacturing method including the step of forming a semiconductor device electrode along with more than one wiring layer connected thereto as well as a method of forming wiring layer.
BACKGROUND OF THE INVENTION
In the recent years it is becoming more important for semiconductor integrated circuit (IC) devices to meet endless demands for device miniaturization with higher integration density, which in turn wiring layers to drastic advances in microfabrication technology of metal oxide semiconductor (MOS) transistors for use with such ICs. Typically, one prior known MOS transistor includes a gate electrode formed on the main surface of a semiconductor substrate with a gate insulator layer laid therebetween, and a pair of spaced-apart source and drain electrodes formed in the main surface of the semiconductor substrate in a manner such that these are self-aligned with the gate electrode. The gate electrode and source/drain electrodes are such that each is connected to its overlying chip wiring layer through a conductive through hole in an interlayer dielectric film sandwiched between the electrode and the wiring layer for electrical connection to active and/or passive IC components operatively associated therewith. Such “internal” chip wiring layer are typically achieved by first forming in an overlying interlayer insulator a contact hole coupled to an associative wiring layer or electrode in an underlying layer, then forming a conductive connector material buried in the contact hole, and further forming an upper wiring layer connected to the conductor. The lower wiring layer and electrode are photolithographically fabricated using photo-etching process into a predefined pattern. Preferably, the pattern of contact holes connected thereto is formed by photo-etching alignment process so that the pattern is accurately aligned in position with those wiring layers in a low-level layer. It is also preferable that these contact holes thus formed are position-aligned with and appropriately connected to their overlying wiring layers in the upper level layer, through a similar position alignment procedure.
Unfortunately, semiconductor technologies are faced with difficulties in achieving precise position alignment between different patterns at different levels over a chip substrate, which would result in occurrence of pattern misalignment. This wiring layers to the risk of short-circuiting between unintentional short of wiring layers and electrodes. To avoid this, an extra area must be consumed as an alignment margin on the substrate surface. One example is that while the use of photo-lithography's minimal fabricatable size permits microfabrication of a rectangular or square contact hole to the extent that it measures 0.1 &mgr;m in side length, addition of such “extra” alignment margin thereto results in an increase in “net” side length of underlying electrodes and wiring layers up to 0.5 &mgr;m or wider.
Hence, providing the alignment margin per pattern serves as a serious bar to successful achievement of microfabrication or “down-sizing” of ICs as required.
Another problem encountered with the prior art approach is that the underlying wiring layers and electrodes of an increased pattern width due to addition of the alignment margin come with a parasitic resistance and parasitic capacitance, which can deteriorate high-speed characteristics of IC components.
One proposed approach for avoiding the problems associated with the prior art is to employ a self-aligned contact (SAC) structure, wherein contact holes are formed in self-alignment with electrodes and wiring layers in a lower layer.
Some prior art MOS transistor structures are shown in
FIGS. 1
a
to
1
c
, wherein each transistor has contact holes H as formed by the SAC technique and connected to source/drain electrodes
15
.
A respective one of the prior art MOS transistor shown in
FIGS. 1
a
-
1
c
is within one of element regions on the main surface of a semiconductor substrate
10
, which regions are electrically insulated from each other by an element isolation region
11
as formed on the substrate surface. The MOS transistor consists essentially of a gate oxide film
12
, a gate electrode
13
, gate-sidewall dielectric films
14
on the opposite sidewalls of gate electrode
13
, and source/drain electrodes
15
as formed by ion implantation with the gate electrode
13
and gate-sidewall dielectric films
14
being as a mask. An interlayer insulator
16
is formed on the surface of the MOS transistor, which film may be a fluorine doped low-dielectric-constant silicon oxide film or the like. Contact holes H are defined in the interlayer insulator
16
, wherein contact wiring layers (not shown in the Fig.) are formed in these contact holes H for electrical connection of the source/drain electrodes
15
and gate electrode
13
to their associated wiring layers on the interlayer insulator
16
.
FIG. 1
a
depicts the cross-sectional structure of one exemplary prior art MOS transistor, wherein misalignment results in one of the contact holes H being laterally offset exposing the sidewall of one gate-sidewall dielectric film
14
as shown. By forming the gate-sidewall dielectric film
14
using a silicon nitride film or the like which has a specified etching selection ratio with respect to silicon oxide of the interlayer insulator
16
, it is possible to leave the gate-sidewall dielectric film
14
, which in turn makes it possible to eliminate unwanted conduction with the semiconductor substrate
10
in those regions other than the intended regions. However, sufficient prevention of such conduction requires formation of the sidewall dielectric film
14
to a thickness greater than a standard thickness, which would result in contradiction with the device miniaturization or microfabrication of MOS tansistors required.
See
FIG. 1
b
. This illustrates in cross-section another prior art MOS transistor structure, wherein misalignment causes one contact hole H to be offset rightward extending so that it rides on a local oxidation of silicon (LOCOS) element isolation region
11
. Such offset of contact hole H toward the element isolation region
11
makes it impossible to prevent the element isolation region made of a silicon oxide film or the like from being partly etched away at its periphery D. This would result in an increase in current leakage between the semiconductor substrate
10
and a contact wiring layer being formed within the offset contact hole H. To avoid this problem, a scheme has been proposed for additionally doping an impurity of the same conductivity type as that of source/drain electrodes
15
by ion implantation into a selected region beneath the etching-removed element isolation region's periphery D to thereby extend the source/drain electrodes
15
. However, this approach suffers from a problem that a leak current can flow between the source/drain and the neighboring semiconductor device components if such extension of the source/drain electrodes
15
renders narrower the element isolation region
11
to the extent that the resulting width is approximately 0.5 &mgr;m or less.
See
FIG. 1
c
, which shows a still another prior art MOS transistor employing a shallow trench isolation (STI) structure for use as the element isolation film as in the previous LOCOS element isolation region shown in
FIGS. 1
a
-
1
b
, wherein misalignment results in one contact hole H being offset toward the side of such STI region
11
a
. The STI region
11
a
can be deeply etched away at its periphery to have a “groove” deeper than the source/drain electrodes
15
. If this is the case, the dielectricity is lowered between the semiconductor substrate
10
and source/drain electrodes
15
causing a problem such as noise generation or the like.
A yet another prior art contact hole formation method is show
Foley & Lardner
Hoang Quoc
Kabushiki Kaisha Toshiba
Nelms David
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