Semiconductor device allowing electrical writing and erasing...

Details Semiconductor device allowing electrical writing and erasing... Semiconductor device allowing electrical writing and erasing...

2000-07-18

2002-03-26

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S588000, C438S593000

Reexamination Certificate

active

06362046

ABSTRACT:

TITLE OF THE INVENTION
Semiconductor Device Allowing Electrical Writing and Erasing of Information and Method of Manufacturing the Same
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, to a semiconductor device allowing electrical writing and erasing of information as well as a method of manufacturing the same.
2. Description of the Background Art
As a kind of semiconductor memory device, there has been known a nonvolatile semiconductor memory device. As a kind of nonvolatile semiconductor memory device, there has been known an EEPROM (Electrically Erasable and Programmable Read Only Memory) in which data can be freely programmed and which allows electrical writing and erasing of information. Although the EEPROM has an advantage that both writing and erasing can be executed electrically, it disadvantageously requires two transistors for each memory cell, and therefore integration to a higher degree is difficult. For this reason, there has been proposed a flash EEPROM including memory cells, each of which is formed of one transistor, and allowing electrical entire chip erasing of written electric information charges. This is disclosed, for example, in U. S. Pat. No. 4,868,619. This flash memory is suitable for high integration because each memory cell is formed of one transistor as described above.
FIG. 25
is an equivalent circuit diagram fragmentarily showing a memory cell array structure of a conventional flash memory. Referring to
FIG. 25
, M
00
-M
35
indicate memory transistors functioning as memory elements. A drain, a gate and a source in each memory transistor are connected to a corresponding bit line (BL
0
-BL
3
), a corresponding word line (WL
0
-WL
5
) and a source line (SL
0
), respectively.
FIG. 26
is a plan showing an actual pattern structure of the memory cell array shown in FIG.
25
. Referring to
FIG. 26
, lines BL
0
-BL
3
, WL
0
-WL
5
and SL
0
correspond to the bit lines, word lines and source line denoted by the same reference characters in FIG.
25
. Element isolating regions
1
are formed at predetermined regions with a predetermined space between each other. Floating gate electrodes
3
are formed at predetermined regions under word lines (WL
0
-WL
5
), and control gate electrodes
5
connected to the word lines are formed on floating gate electrodes
3
. Metal interconnections
8
made of, e.g., aluminum interconnections and forming bit lines (BL
0
-BL
3
) extend perpendicularly to word lines (WL
0
-WL
5
).
FIGS. 27
to
32
are cross sections taken along line
100
—
100
in FIG.
26
and showing the structure during manufacturing in accordance with the order of process steps.
FIGS. 33
to
37
are cross sections taken along line
200
—
200
in FIG.
26
and showing the structure during manufacturing in accordance with the order of process steps. Referring to
FIGS. 27
to
37
, the manufacturing process of the conventional flash memory will be described below.
First, as shown in
FIG. 27
, element isolating regions
1
are formed on a surface of a semiconductor substrate
101
by the LOCOS (LOCal Oxidation of Silicon) method of the like. Then, as shown in
FIG. 28
, first gate oxide films
2
a
are formed, e.g., by the thermal oxidation method on portions of the surface of semiconductor substrate at which element isolating regions
1
do not exist. A polycrystalline silicon film (not shown) is deposited by the CVD (Chemical Vapor Deposition) method, and subsequently is patterned along an extending direction of the word line by the photolithography and dry etching technique. Thereby, first gate electrodes
3
a
are formed. Then, as shown in
FIG. 33
, an interlayer insulating layer
4
a
is formed on first gate electrodes
3
a
by the thermal oxidation method or CVD method. A second gate electrode
5
a
formed of a polycrystalline silicon film or a polycide film (i.e., multilayer film formed of a polycrystalline silicon film and a metal silicide film of a high melting point) is formed on interlayer insulating layer
4
a
by the CVD method. The photolithography and dry etching technique are executed to pattern second gate electrode
5
a
, interlayer insulating layer
4
a
, first gate electrode
3
a
and first gate oxide film
2
a
to extend them perpendicularly to the extending direction of the word line. Thereby, first gate oxide films
2
, floating gate electrodes
3
, interlayer insulating layers
4
and control gate electrodes
5
are formed as shown in
FIGS. 29 and 34
. Thereafter, impurity is ion-implanted into semiconductor substrate
101
to form drain regions
13
and source regions
14
using the control gate electrodes
5
as a mask.
As shown in
FIGS. 30 and 35
, an interlayer insulating layer
6
is formed, e.g., by the CVD method, and contact holes
7
are formed by the photolithography and dry etching technique.
As shown in
FIGS. 31 and 36
, a metal interconnection layer (not shown) made of, e.g., aluminum alloy is formed on the whole surface by the sputtering method or the like, and subsequently is patterned by the photolithography and dry etching technique. Thereby, metal interconnection layers
18
forming the bit lines and source line are formed.
As shown in
FIGS. 32
to
37
, a surface protective film
9
is formed by the CVD method. Surface protective film
9
covers portions other than bonding pad connections (not shown). In this manner, the conventional flash memory is completed.
Operation of the conventional flash memory will be described below. The flash memories of 1 to 8 megabits which are now available are operated by the CHE injection writing, i.e., writing by injection of channel hot electrons and the tunnel erasing, i.e., tunnel removal thereof from a source. As another method of writing and erasing in the flash memory, the tunnel writing and tunnel erasing may be employed, by which both writing and erasing are carried out with a tunnel current.
FIG. 38
shows a concept of variation of memory transistor characteristics caused by writing and erasing.
FIG. 39
shows a concept of writing of a flash memory by the CHE injection.
FIG. 40
shows a concept of erasing of the flash memory by the tunnel erasing.
For performing writing by the CHE injection, semiconductor substrate
101
and source region
14
of the memory transistor, on which writing is effected, are grounded as shown in
FIGS. 38 and 39
. A voltage Vd from 5V to 8V is applied to drain region
13
via the bit line. A voltage Vg from 10V to 13V is applied to control gate electrode
5
via the word line. Thereby, hot electrons generated by high electric charges near the drain are injected into floating gate electrode
3
. By maintaining the electrons in floating gate electrode
3
, the threshold voltage of memory transistor is shifted, so that the writing is completed.
The writing can be performed in either a timing mode similar to that of the conventional EPROM or a command mode in which a chip internally and automatically performs the writing in accordance with a command and a data applied thereto. In either mode, a write depth at the written position is generally verified, and, if shallow, additional writing is effected. More specifically, as shown in
FIG. 41
, a write pulse is applied at step S
1
, and write verification is performed at subsequent step S
2
. If the result of write verification represents the shallow write, the process returns to step S
1
for additional writing. If the result of write verification represents the sufficient writing, the writing is completed as indicated at step S
3
.
The tunnel erasing will be described below with reference to
FIGS. 38 and 40
. For the tunnel erasing, drain region
13
is set to a floating state, and control gate electrode
5
and semiconductor substrate
10
are grounded. A high voltage Vs, e.g., from 8V to 12V is applied to source region
14
. In this case, the potential of floating gate electrode
3
depends on the potential set by electrons in floating gate electrode
3
as well as

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