Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-08-18
2002-01-15
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S228000
Reexamination Certificate
active
06339552
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique for inputting information which is suitable for use in a semiconductor device supplied with the information, e.g., a technique effective for application to a DDR (Double Data Rate)-operable SDRAM (Synchronous Dynamic Random Access Memory).
With the speeding up of operation, an external interface such as an SDRAM is now migrating toward a small-amplitude signal interface like SSTL (Stub Series Terminated Transceiver Logic). A differential amplifier circuit provided with a current mirror load has widely been adopted for an input buffer of the SSTL specs-based interface. Since a through current always flows in the differential amplifier circuit in an active state, the differential amplifier circuit increases power consumption as compared with a CMOS input buffer comprising a complementary type MOS circuit, but is capable of receiving a small signal therein at high speed.
In a synchronous memory like the SDRAM, timing provided to operate it is controlled based on an external clock signal like an externally supplied system clock signal, This type of synchronous memory has the feature that the setting of internal operating timings by the use of the external clock signal becomes relatively easy and a relatively high-speed operation is made possible.
As the SDRAM used herein, there are known a so-called SDR (Single Data Rate) type SDRAM wherein the input and output of data are performed in synchronism with the rising edge of an external clock signal, and a so-called DDR type SDRAM wherein the input and output of data are carried out in synchronism with both the rising and falling edges of an external clock signal.
SUMMARY OF THE INVENTION
The SDR type SDRAM and the DDR type SDRAM are different from each other in terms of input timing control for writing data. The supply of data from the outside in a clock signal cycle identical to that for external instructions for a write operation is defined or provided for the SDR type SDRAM. Since instruction for a write operation by a write command following a bank active command is provided and simultaneously write data is supplied, the activation of a data input buffer after the reception of the write command will not suffice for the input of the write data supplied in synchronism with the clock signal together with the write command. Thus, the data input buffer is activated when it has accepted a bank active command for providing instructions for the operation of a row address system.
On the other hand, the supply of data from the outside, synchronized with a data strobe signal as viewed from a clock signal cycle subsequent to a clock signal cycle at which external instruction for a write operation is provided, is defined or provided for the DDR type SDRAM. The data strobe signal is used even for data output. The use of such a data strobe signal and the proper setting of a delay in propagation of data and a delay in propagation of the data strobe signal to each individual SDRAM on a memory board relatively facilitate a reduction in variations in distance-dependent time required to access data from a memory controller to each SDRAM on the memory board.
The present inventors have discussed control on the activation of the data input buffer employed in the DDR type SDRAM. According to their discussions, it has been revealed by the present inventors that when the data input buffer is activated in response to a bank active command in a manner similar to the SDR type even in the case of the DDR type SDRAM, the data input buffer is subsequently kept in an active state until a precharge command is accepted, for example, and the data input buffer wastefully consumes or uses up power during a period in which a write command is issued after the bank active command. It has also been revealed by the present inventors that the write command is not necessarily issued after the bank active command, and when no write command is issued, the activated state of the data input buffer comes to nothing as a consequence and the power consumed by the data input buffer is entirely wasted. The adoption of an SSTL interface for the data input buffer of the DDR-SDRAM is defined or provided by JEDEC (Joint Electron Device Engineering Council). It has been found out by the present inventors that if a case which complies with this definition is taken into consideration, then control timing provided to activate the input buffer of the SSTL interface leads to a large element with a view toward achieving low power consumption of the DDR-SDRAM.
An object of the present invention is to provide a semiconductor device capable of reducing the consumption of power by an external interface buffer such as a data input buffer or the like.
Another object of the present invention is to provide a semiconductor device suitable for use in a DDR type SDRAM which has planned low power consumption.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
A summary of a typical one of the embodiments disclosed in the present application will be described in brief below.
In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state and an active state after having accepted instruction for writing of the data into the memory unit.
Although not restricted in particular, the semiconductor device may be a clock synchronous semiconductor device such as an SDRAM, which performs the operation of writing data into a plurality of memory cells and the operation of reading data therefrom in response to a clock signal.
The data input buffer is a differential input buffer having interface specs based on an SSTL standard, for example. The corresponding buffer is brought to an active state by the turning on of its power switch and brought to an inactive state by the turning off thereof. The input buffer typified by the differential input buffer allows a through current to flow in its active state and is capable of immediately following even a small change in a small-amplitude input signal and transferring the input signal to a subsequent stage.
Since such an input buffer is brought to the active state only when instruction for the writing of the data into the memory unit is given thereto, wasteful power consumption that would occur by the data input buffer being brought to the active state in advance before the instruction for the write operation is provided, is avoided.
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Horiguchi Masashi
Miyashita Hiroki
Shibata Ken
Taruishi Binhaku
Hitachi , Ltd.
Miles & Stockbridge P.C.
Nguyen Tan T.
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