Semiconductor device

Details Semiconductor device Semiconductor device

2001-01-05

2002-01-08

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230080, C365S189011

Reexamination Certificate

active

06337812

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, more particularly to a field memory that is used for memorizing picture data (one screen) for displaying on a display screen.
2. Description of Related Art
FIG. 2
is a block diagram showing an example of the conventional field memory.
This field memory includes a Y decoder
30
S, a shift redundancy circuit
20
S, and a sub-register block
10
S for storing the picture data for the first row of the display screen, a memory cell block
40
for storing picture data after the second row, and so forth.
The sub-register block
10
S includes m+1 registers including an auxiliary to the number m (m is an integer) of pictures for one row of the display screen. The Y decoder
30
S selects one of the m column lines by decoding a column address signal ADY and outputs a column signal when an enabling signal SEN for a sub-register block is provided at the time of displaying the first row. The input side of a shift redundancy circuit
20
S is connected to the m column lines. Here, the enabling signal SEN is a signal for indicating the picture element position of the picture data, and indicates the first row of the picture data as the top portion.
The shift redundancy circuit
20
S corresponds between the m column lines and the m+1 registers of the sub-register block
10
S. The shift redundancy circuit
20
S includes a fuse group for changing connection and a switch group for changing a connection condition based on the condition of this fuse group. For the shift redundancy circuit
20
S, in the condition where all the fuses are not cut off, each of the first to m-th input sides is connected to each of the first to m-th output sides. Further, when an i-th (i is a positive integer below m) fuse is cut off, each of the first to i−1-th input sides is connected to each of the first to i−1-th output sides in a direct manner, and each of the i-th to m-th input sides is connected to each of the i+1 to m+1-th output sides by shifting one respectively. Accordingly, when the i-th register of the sub-register block
10
S is broken, the broken fuse can be disregarded by cutting off the i-th fuse of the shift redundancy circuit
20
S.
On the other hand, the memory cell block
40
memorizes the picture data of the second to n-th (n is a positive integer greater than 2) row. The memory cell block
40
is composed of n−1 word lines arranged in a parallel way, m+1 bit lines arranged in a crossing way thereto, and respective memory cells arranged in respective crossing points between such respective word lines and such bit lines. The word line of the memory cell block
40
is connected to an X decoder
50
that decodes a row address signal ADX and drives the corresponding word line. For the memory cell block
40
, when one word line is driven by the X decoder
50
, each of the m+1 memory cells corresponding thereto is selected and connected to each corresponding bit line.
The resister block
10
R is connected to the m+1 bit lines of the memory cell block
40
using a sense amplifier block
60
. A sense amplifier block
60
amplifies a tiny potential difference, which is output to respective bit lines from the memory cell of the memory cell block
40
at the time of a read-out operation, until the predetermined logical level is attained. The resister block
10
R temporarily memorizes data, which is read and/or written to the memory cell of the memory cell block
40
, one line at a time. In the same way as the sub-register block
10
S, the column signal is provided to the resister block
10
R based on the column address signal ADY from a Y decoder
30
R using a shift redundancy circuit
20
R.
A read write (R/W) buffer
70
S that performs write-in or read-out to a register, which is selected sequentially by the column signal, is connected to the sub-register block
10
S. In the same way, a read write buffer
70
R that performs write-in or read-out to a register, which is selected sequentially by the column signal, is connected to the register block
10
R. The read write buffers
70
S and
70
R are connected to selectors
80
and
90
. As a result, write-in data DTW is provided from the outside through the selector
80
, and read-out data DTR is output to the outside through the selector
90
.
In such a field memory, it is tested whether or not write-in or read-out is performed to the sub-register block
10
S register at the stage of manufacturing and it is checked whether or not a failure condition has occurred. If the failure register is found in the checked registers, the fuse corresponding thereto of the shift redundancy circuit
20
S is cut off and then the failure register thereof is eliminated. Further, it is tested whether or not write-in or read-out is performed to the memory cell of the memory cell block
40
and it is checked whether or not the failure has occurred. If the failure memory cell is found in the memory cell block, the fuse corresponding thereto of the shift redundancy circuit
20
R is cut off and the failure memory cell thereof is then eliminated.
In this field memory, the data write-in is performed in the following way. When m data of the first column of the display screen is written in, the selector
80
is switched towards the read write buffer
70
S. Further, the enabling signal SEN for the sub-register block is provided to the Y decoder
30
S, the column address signal ADY is decoded by this Y decoder
30
S, and then the column signal is provided to the sub-register block
10
S by way of the shift redundancy circuit
20
S.
On the other hand, the write-in data DTW is provided to the sub-register block
10
S by way of the selector
80
. Accordingly, the write-in data DTW provided to the column address signal ADY in a synchronizing manner is written sequentially in respective registers of the sub-register block
10
S.
When the data after the second row of the display screen is written in, the selector
80
is switched towards the read write buffer
70
R. Further, the enabling signal REN for the register block is provided to the Y decoder
30
R, the column address signal ADY is decoded by this Y decoder
30
R, and then the column signal is provided to the resister block
10
R using the shift redundancy circuit
20
R. The enabling signal REN is a signal for indicating the picture element position of the picture data and indicates the picture data other than the top position, namely after the second row.
On the other hand, the write-in data DTW is provided to the resister block
10
R through the selector
80
. Accordingly, the write-in data DTW that is provided by synchronizing with the column address signal ADY is written sequentially in respective registers of the resister block
10
R. When the write-in data DTW for one row is stored in respective registers of the resister block
10
R, the contents of respective registers of this resister block
10
R are output to the memory cell block
40
by way of the sense amplifier block
60
and the bit lines. Accordingly, the write-in data DTW for one row is written simultaneously in the memory cell connected to the word line selected by the X decoder
50
.
Further, in this field memory, the data read-out is performed in the following way. When m data of the display screen is read out, the selector
90
is switched towards the read write buffer
70
S. Further, the enabling signal SEN is provided to the Y decoder
30
S, the column address signal ADY is decoded by this Y decoder
30
S, and then the column signal is provided to the
30
sub-register block
10
S using the shift redundancy circuit
20
S.
Accordingly, the contents of respective registers of the sub-register block
10
S are readout sequentially by synchronizing with the column address signal ADY, and then the read-out data DTR is output from the selector
90
.
When the data after the second row of the display screen is read out, the selector
90
is switched towards the read write buffer
70
R. Further, the contents of the memor

Affiliated with

Also associated with

Rating

Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2818839