Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2008-07-08
2008-07-08
Parekh, Nitin (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S773000, C257S778000
Reexamination Certificate
active
07397138
ABSTRACT:
Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.
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Japanese Office Action issued in corresponding Japanese Patent Application No. JP 2003-087824, dated Jan. 4, 2007.
Doi Atsushi
Huh Hoyeun
Nagai Noriyuki
Nakayama Tomoyuki
Ohnishi Manabu
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
Parekh Nitin
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