Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-04-12
2011-04-12
Dole, Timothy J (Department: 2858)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S537000, C714S719000, C714S724000
Reexamination Certificate
active
07925944
ABSTRACT:
In a semiconductor device including an N-line M-stage shift register circuit operated at high speed of, for example, several hundreds MHz. Input circuits input a common test pattern to each of pairs of shift registers in, for example, two lines out of the N lines. A plurality of outputs of the pairs of shift registers in the two lines are compared in comparators, and the comparison results are output. The N-line M-stage shift register circuit and the comparators are operated in synchronization with a clock signal at several hundreds MHz. Hence, even when the circuit scale (area) of the N-line M-stage shift register circuit is increased to involve apparent wiring delay, a defect in the shift register circuit can be detected at an actual speed.
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Daio Kinya
Hirose Masaya
Watanabe Kenji
Yamamoto Takeshi
Baldridge Benjamin M
Dole Timothy J
McDermott Will & Emery LLP
Panasonic Corporation
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