Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2011-08-09
2011-08-09
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
07996735
ABSTRACT:
To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.
REFERENCES:
patent: 5254382 (1993-10-01), Ueno et al.
patent: 5883827 (1999-03-01), Morgan
patent: 7075140 (2006-07-01), Spadea
patent: 7438965 (2008-10-01), Ohkura et al.
patent: 7573058 (2009-08-01), Noh et al.
patent: 7692979 (2010-04-01), Fuji et al.
patent: 7777213 (2010-08-01), Kang et al.
patent: 2003/0002367 (2003-01-01), Hong et al.
patent: 2007/0248785 (2007-10-01), Nakai et al.
patent: 2009/0073753 (2009-03-01), Osada et al.
patent: 2002-109797 (2002-04-01), None
patent: 2003-100991 (2003-04-01), None
patent: 2005-050424 (2005-02-01), None
patent: 2003-0002419 (2003-01-01), None
Stefan Lai et al, “OUM—A 180 nm Nonvolatile Memory Cell Element Technology For Stand Alone and Embedded Applications”, IEEE, IEDM pp. 803-806, 2001.
Martijn H .R. Lankhorst et al, “Low-cost and nanoscale non-volatile memory concept for future silicon chips”, Nature Materials, vol. 4, pp. 347-352, 2005.
Myoung-Jae Lee et al, “2-Stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications”, IEEE, IEDM pp. 771-774, 2007.
Hanzawa Satoru
Kinoshita Masaharu
Kume Hitoshi
Ogushi Minoru
Sasago Yoshitaka
Hitachi , Ltd.
Miles & Stockbridge P.C.
Ton David
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