Semiconductor device

Details Semiconductor device Semiconductor device

2000-09-21

2001-10-23

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230080, C365S189110, C326S030000

Reexamination Certificate

active

06307791

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims benefit of priority under 35 USC 119 based on Japanese patent application PH11-269520 filed Sep. 22, 1999, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and particularly, to a semiconductor device having an output impedance controller that controls the impedance of an output buffer with the use of an external resistor.
2. Description of Related Art
Improving MPU performance is requiring memories of faster data transfer rates. For example, external cache memories are required to operate at several hundred megahertz.
To realize such high-frequency data transfer from a memory to an MPU, the impedance of an output buffer of the memory needs to be matched with the impedance of a board data bus in consideration of data bus conditions such as signal reflection. The higher the operating frequency, the more the accuracy of impedance matching is required. To achieve this, a technique of correcting impedance errors caused by various factors is used.
In this technique, drive ability is adjusted to the predetermined value to change the size of transistors, i.e., the impedance of an output buffer of a memory if the characteristics of the transistors deviate from required ones due to manufacturing variations or varying operation conditions including operation temperatures and voltages. This technique is called a programmable impedance control function.
FIG. 1
shows a circuit according to a prior art for achieving the programmable impedance control (The source “Digest of Tech papers (IEEE) Feb. 8, 1996: ISSCC96 Page 148”). This circuit includes an output buffer
111
and an output impedance controller, which consists of elements
112
to
120
to control the output impedance of the output buffer
111
. An external resistor RQ is selected as an impedance source according to which the impedance of the output buffer
111
is adjusted. The resistor RQ is connected to a ZQ-terminal. The output impedance controller controls the number of active transistors in the output buffer
111
, to match the output impedance of the output buffer
111
with the impedance of the resistor RQ.
In
FIG. 1
, the output impedance controller includes an evaluation unit
112
, a comparator
113
, an up/down (U/D) counter
114
, registers
115
to
117
, a selector
118
, a data update controller
119
, and a clock generator
120
.
The evaluation unit
112
has a reference current source consisting of an NMOS transistor
112
a
and resistors R
0
and R
1
, and a dummy buffer consisting of transistors
1
X,
2
X,
4
X, and
8
X. The number of transistors in the dummy buffer is equal to or a multiple of the number of transistors in the output buffer
111
. The reference current source generates a voltage VZQ for the ZQ-terminal and a voltage VEVAL for the dummy buffer. The voltages VZQ and VEVAL are transferred to the comparator
113
. The output of the comparator
113
controls the counter
114
, which turns on and off the NMOS transistors
1
X to
8
X of the dummy buffer to equalize the voltages VZQ and VEVAL.
In this way, the impedance of the dummy buffer is matched with that of the resistor RQ.
Data used to adjust the impedance of the dummy buffer in accordance with the resistor RQ is transferred to the output buffer
111
through the data update controller
119
. Based on the data, drive transistors
1
Y to
8
Y and
1
Z to
8
Z of the output buffer
111
are selectively turned on and off to equalize the impedance of the output buffer
111
with the impedance determined by the resistor RQ.
In
FIG. 1
, the pull-up and pull-down sides of the output buffer
111
consist each of NMOS transistors, and therefore, manufacturing variations and operating variations on these transistors are equal. Accordingly, the dummy buffer may have a single system of NMOS transistors to control the ON/OFF states of the transistors of the output buffer
111
.
If the pull-up side of the output buffer
111
is made of PMOS transistors, the dummy buffer must additionally have a system of PMOS transistors to adjust the impedance of the output buffer
111
because PMOS transistors involve different manufacturing variations from NMOS transistors.
FIG. 2
shows an output impedance controller according to a related art, for adjusting the impedance of two systems in a programmable impedance output buffer.
The output impedance controller has a reference current source
211
that includes a reference voltage generator
221
. The reference voltage generator
221
uses a voltage VDDQ that is between a high voltage VDD and a low voltage VSS to apply a fixed voltage to a ZQ-terminal. The reference voltage generator
221
has voltage dividing resistors Ra and Rb and an activation NMOS transistor N
20
and generates a reference voltage VDDQ/2. The reference voltage VDDQ/2 is applied to a noninverted input terminal of an operational amplifier OP
1
. The output of the operational amplifier OP
1
controls an NMOS transistor N
21
whose source is fed back to an inverted input terminal of the operational amplifier OP
1
. As a result, the ZQ-terminal receives the reference voltage VZQ=VDDQ/2.
The reference voltage VZQ is applied to the ZQ-terminal so that a current IZQ flows through an external resistor RQ connected to the ZQ-terminal. The current IZQ is a reference current representing the resistance of the resistor RQ. PMOS transistors P
21
and P
23
form a current mirror circuit that forms a current feed source
222
to feed a current from the power source VDD to a pull-down dummy buffer Ndm according to the reference current IZQ.
A current mirror circuit consisting of the PMOS transistors P
21
and P
22
and a current mirror circuit consisting of NMOS transistors N
22
and N
23
connected to the output of the current mirror circuit of P
21
and P
22
form a current pull-in source
223
that pulls a current from a pull-up dummy buffer Pdm into the power source VSS.
The output impedance controller also has a pull-down controller
213
. The pulldown controller
213
has an operational amplifier OP
2
to receive a voltage from a connection node REFIU and the voltage VZQ from the ZQ-terminal, and a U/D counter
224
for carrying out up/down counting in response to the output of the operational amplifier OP
2
. The output impedance controller also has a pull-up controller
215
. The pull-up controller
215
has an operational amplifier OP
3
to receive a voltage from a connection node REFID and the voltage VZQ from the ZQ-terminal, and a U/D counter
225
for carrying out up/down counting in response to the output of the operational amplifier OP
3
.
The pull-down dummy buffer Ndm has N pieces of NMOS transistors (N
31
to N
33
in FIG.
2
). The drains of the transistors N
31
to N
33
are commonly connected to the connection node REFIU. The sources of the transistors N
31
to N
33
are commonly connected to the power source VSS, and the gate widths of these transistors are set as, for example, 1:2:4.
The counter
224
provides N pieces of output bits D
0
to Dn−1 that are supplied to the gates of the transistors N
31
to N
33
, respectively. The pull-down controller
213
determines the ON/OFF states of the transistors N
31
to N
33
so that a voltage at the connection node REFIU may agree with the voltage VZQ, thereby determining the impedance of the dummy buffer Ndm.
The pull-up dummy buffer Pdm has M pieces of PMOS transistors (P
31
to P
33
in FIG.
2
). The drains of the transistors P
31
to P
33
are commonly connected to the connection node REFID. The sources of the transistors P
31
to P
33
are commonly connected to the power source VDDQ, and the gate widths of these transistors are set as, for example, 1:2:4.
The counter
225
provides M pieces of output bits U
0
to Um−1, which are supplied to the gates of the transistors P
31
to P
33
, respectively. The pull-up controller
215
determines the ON/OFF states of the transistors P
31
to P

Affiliated with

Also associated with

Rating

Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2603297