Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-29
2001-11-06
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S355000, C257S371000, C257S544000
Reexamination Certificate
active
06313511
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to semiconductor devices, and more particularly, to circuitry for measurement of a threshold voltage variation or deviation during manufacture of metal insulator semiconductor field effect transistor (MISFET) integrated circuits and the driving methodology thereof, and circuitry for use in reducing any undesired threshold voltage variation.
2. Description of the Related Art
Integrated circuit (IC) devices with a plurality of MISFET transistors integrated on a semiconductor substrate tend to exhibit an increase in a difference between a maximal value of threshold voltage and a minimal threshold voltage with an increase in number of integrated transistors, because such plural transistors can statistically vary or change in threshold voltage level. One typical prior known approach to reduce or suppress such threshold voltage variation is to employ a method including the steps of measuring a variation in threshold voltage of the individual transistor and then letting a substrate bias of each transistor change for threshold voltage correction, thereby permitting equalization or alignment of threshold voltages among the transistors that are involved.
Unfortunately, a problem associated with the related art approach is that in cases where transistor variation lacks any specific positional dependence and thus remains random in the position, sets of electrical wiring associated with a substrate biasing circuit that are required for the intended threshold voltage correction must increase in number up to the requisite number of transistors, resulting in a significant increase in the wiring when compared to the case of elimination of such threshold voltage correction. Another problem faced with this conventional method is that it requires an extra circuit for threshold voltage correction in an analog fashion or alternatively additional effectuation of trimming processes, which results in an unwanted increase in the area of the correction circuit.
Furthermore, related art threshold voltage measurement circuitry typically uses an increased number of input/output terminals that is greater than or equal to a square root of transistors under measurement, and the terminals are formed at specific locations outside of a transistor array. Accordingly, the amount of wiring likewise increases, thus making it difficult to reduce or “shrink” the area of input/output terminals used for threshold voltage measurement.
FIGS. 18A and 18B
are schematic diagrams depicting one exemplary related art transistor array for use in measuring a threshold voltage variation. Reference characters “Q
ab
” (where the suffices “a” and “b” are natural numbers) are used to designate transistors; white circular or balloon-like markings as used herein denote terminals Nc, wherein the reference number of such terminals is indicated by the suffix “c” (where c is a natural number). Here, certain transistors under measurement of threshold voltages are called the “select” transistors, whereas the remaining transistors that are not related to such threshold voltage measurement are called “no select” or “non-select” transistors.
The circuit of
FIG. 18A
includes a parallel combination of transistors Q
1
to Q
n
with their sources and drains connected in parallel together, and is operable to measure a threshold voltage(s) through measurement of a current flowing between a source electrode and a drain electrode while causing a gate voltage of a select transistor to change in potential level with a gate voltage of a non-select transistor being kept less than or equal to its threshold voltage. In this case, an input to a respective gate terminal is subdivided in order to select the individual transistor; for completion of measurement of threshold voltages of n transistors, the number of terminals that are provided must be at least (n+2).
On the other hand, the circuit of
FIG. 18B
is the circuit that includes an array of measurement transistors arranged in the form of a two-dimensional (2D) matrix. More specifically, this circuit includes transistors Q
1b
to Q
nb
which have their sources and drains serially coupled together, and is operable to measure threshold voltages or values by applying a specified voltage to allow a gate voltage of a nonselect transistor to be greater than the threshold voltage thereof to thereby potentially change the gate voltage of a select transistor for measurement of a current flow between a terminal N
n+b
and a terminal N
2n+1
. In this method also, a specified number—at least (2n+1) or greater—of terminals must be provided with respect to the n
2
transistors.
A further problem associated with the related art is that a transistor array structure with a gate and source/drain being electrically separated or isolated by the individual transistor requires fabrication of a gate wiring between source/drain wiring, which can result in an increase in wiring area.
On the other hand, integrating measurement circuitry including but not limited to an address decoder for transistor selection on the same semiconductor chip, together with a transistor array for threshold voltage measurement, allows the reduction of the requisite number of those terminals that are provided outside of the semiconductor chip.
Regrettably, the related art remains incapable of measuring threshold voltages of certain transistors forming the address decoder circuit. Therefore, it is impossible or at least very difficult to compensate for the threshold voltage of a transistor circuit at this part, because wiring creates a problem of increasing circuit area. In addition, the resulting circuit layout can significantly change due to the presence of wiring between such measurement circuitry and transistor array and also between a substrate bias circuit and the transistor array when compared to the case of eliminating the circuits of any threshold voltage correction, which disadvantageously requires large-scale modification or alteration of the circuit layout.
A still further problem associated with the circuits shown in
FIGS. 18A and 18B
is that measurement of threshold voltages of n transistors calls for recurrent measurement processes for respective transistors on a one-by-one basis, and results in an extreme increase in measurement time duration with an increase in the number of transistors used.
As has been described above, a significant problem associated with the related art circuits is that the procedure for correction of threshold voltages of n transistors causes the requisite number of associative terminals to increase beyond the transistor number, n, resulting in an increase in the area of circuitry.
SUMMARY OF THE INVENTION
The present invention as disclosed and claimed herein has been made in order to avoid the problem faced with the related art, and a primary object of the present invention is to provide a new and improved semiconductor device having threshold voltage measurement circuitry that eliminates a need to significantly modify a circuit layout with respect to those circuits with no concern to the threshold voltage correction and also having circuitry for suppressing a variation in threshold voltage.
To attain the foregoing object the present invention provides a semiconductor device comprising a semiconductive substrate; a first substrate conductor region formed on or over the substrate and commonly shared by a first plurality of metal insulator semiconductor field effect transistors (“MISFETs”); a second substrate conductor region formed on or over the substrate and commonly shared by a second plurality of MISFETs; a third substrate conductor region formed on or over the substrate and commonly shared by a third plurality of MISFETs; a first power supply node having an output connected to the first substrate conductor region; a second power supply node having an output connected to the second substrate conductor region; a third power supply node having an output connected to the third substrate conductor
Anya Igwe U.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Smith Matthew
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