Semiconductor device

Details Semiconductor device Semiconductor device

1998-10-22

2001-09-04

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06286121

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a logic unit, a storage unit, and a built-in self test (BIST) circuit, and particularly to improvement for preventing test by the BIST circuit from being interfered with by initial undefined value stored in the storage unit with simple structure.
2. Description of the Background Art
FIG. 10
is a block diagram showing the structure of a conventional semiconductor device as a background of the present invention. This semiconductor device
151
is constructed as a dedicated LSI for specific applications called ASIC (Application-Specific IC), which includes a RAM
10
as a storage unit and combinational logic circuits
40
,
41
, and
42
as logic units at the same time. It further includes a BIST circuit for executing BIST so as to easily and efficiently perform test to the ASIC formed as a VLSI with highly integrated circuit elements. The BIST is a method for facilitating test to semiconductor devices in which semiconductor devices are tested by themselves.
The BIST circuit has an LFSR (Linear Feedback Shift Register)
50
and an MISR (Multiple Input Signature Register)
51
, and it also uses the scan test method. That is to say, storage elements such as flip-flops provided in peripheral parts of the RAM
10
and the combinational logic circuits
40
,
41
,
42
to achieve original functions of the device
151
(functions other than testing) are coupled in cascade in a freely coupled/decoupled manner to form scan paths
11
to
14
, and
21
to
24
.
The scan path
23
is located in the peripheral part of the combinational logic circuit
40
. It is formed by coupling storage elements that exchange signals with the combinational logic circuit
40
. Similarly, the scan path
24
is located in the peripheral part of the combinational logic circuits
41
and
42
, which is formed by coupling storage elements that exchange signals with them.
The scan path
21
is formed by coupling storage elements interposed between the combinational logic circuit
40
and the combinational logic circuit
41
for exchanging signals, and the scan path
22
is formed by coupling storage elements interposed between the combinational logic circuit
40
and the combinational logic circuit
42
for exchanging signals. The scan paths
11
to
14
are each formed by coupling storage elements interposed between the RAM
10
and the combinational logic circuit
40
for exchanging signals between them.
These storage elements are coupled to each other only when test is performed, and they are decoupled in other operations. The BIST circuit performs test to the RAM
10
and the combinational logic circuits
40
,
41
,
42
in the device
151
through these scan paths
11
to
14
,
21
to
24
. The scan paths
21
,
11
to
14
,
22
are coupled to form one row of scan path. Three rows of scan paths, the scan path
23
, the scan path
21
,
11
to
14
,
22
, and the scan path
24
, are interposed between the LFSR
50
and the MISR
51
.
Usually, the storage elements like the FFs (flip-flops) forming the scan paths are elements provided in peripheral parts in logic units and storage units, to function as relay for exchange of signals with other units. That is, the storage elements forming the scan paths usually belong to some one of the units. For example, the part surrounded by the dotted line marked “1” in
FIG. 10
corresponds to the original storage unit. However, for the purpose of clearly showing the relation between the scan paths and other parts, this specification defines the parts other than the scan paths as the combinational logic circuits (logic units)
40
,
41
,
42
, and RAM (storage unit)
10
, as shown in the drawings including FIG.
10
.
FIG. 11
is a block diagram showing the inside structure of the LFSR
50
. The LFSR
50
includes a plurality of FFs
61
coupled in cascade to each other and an EXOR (exclusive OR element)
62
for connecting them in a circulating manner. The FFs
61
hold and output input signals in synchronization with a clock signal (not shown). Accordingly after the FFs
61
have been supplied with given initial value for initialization, pseudo-random numbers with circulating period determined by the number of FFs
61
coupled in cascade sequentially appear at the outputs of the FFs
61
in synchronization with the clock signal and transferred to the following FFs
61
.
In the example shown in
FIG. 11
,
22
FFs
61
are coupled in cascade and therefore 2
22
-1 pseudo-random numbers are periodically generated. Three of the 22 outputs are respectively supplied to the three rows of scan paths. That is, the LFSR
50
is configured as a kind of test pattern generator (TPG) circuit for generating test patterns for BIST and supplying them to a row or a plurality of rows of scan paths.
FIG. 12
is a block diagram showing the internal structure of the MISR
51
. The MISR
51
has a plurality of circuits coupled in cascade each including an FF
63
and an EXOR
64
, and an EXOR
65
for coupling those circuits in a circulating manner. Signals inputted to the EXORs
64
in synchronization with a clock signal not shown are subjected to certain operation, and then the operated signals are outputted from the final-stage FF
63
as signature SO. The signature SO corresponds to a signal obtained by compacting the signals inputted to one or a plurality of EXORs
64
along time series and (in the case of multiple inputs) along the space.
In the example shown in
FIG. 12
,
22
circuits are coupled in cascade, and signals from the three rows of scan paths are supplied to three of the 22 inputs. Then the information about the results obtained by testing the individual parts in the device
151
supplied through the scan paths is integrated into the signature SO. Thus, the MISR
51
is configured as a kind of output data compactor (ODC) circuit for compacting signals containing information about test results supplied from a row or a plurality of rows of scan paths, i.e., signals representing test results.
The signature SO is transferred out of the device
151
through a pin (not shown) to be used as expected value for the test results. A comparison in pattern is made between the normal value for the signature SO obtained by performing logical simulation to the device
151
and the real value of the signature SO held in the MISR
51
to determine whether the combinational logic circuits
40
,
41
,
42
and the RAM
10
, including the scan paths, are normal. In this way, the presence of the BIST circuit enables individual parts in the device
151
to be tested just by comparing the value of signature SO outputted from the device
151
itself with the normal value.
FIG. 13
is a block diagram fully showing the scan paths
13
and
14
interposed between the combinational logic circuit
40
and the RAM
10
. The scan path
13
is formed by coupling three FFs
71
in cascade which are interposed between the combinational logic circuit
40
and the RAM
10
, for receiving signal outputs from the combinational logic circuit
40
and sending them as data signals to data input portions di[n] (n=0, 1, 2) of the RAM
10
.
The FFs
71
are coupled with the respective preceding FFs
71
through selectors
72
. An SFF (scan flip-flop, generally “a scan storage element”)
2
is usually configured by adding a selector
72
required for test to an FF
71
used to allow the device
151
to achieve its original (i.e., designed) function. A plurality of SFFs
2
are coupled in cascade to form the scan path
13
. This structure is the same with other scan paths. The FFs
71
in the SFFs
2
forming the scan path
14
receive data signals (storage data signals) outputted from the data output portions do[n] of the RAM
10
and send them to the combinational logic circuit
40
.
Each selector
72
is responsive to the value of a scan mode signal SM inputted as a select signal to select one of its two input signals. Specifically, when the scan mode signal SM is 0, the sele

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