Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
1999-04-21
2001-01-23
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S048000, C438S612000, C438S666000
Reexamination Certificate
active
06177733
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a measuring element such as TEG (Test Element Group), and more particularly, to a semiconductor device in which an area of a pattern region for a measuring element is reduced.
2. Description of the Related Art
Conventionally, when a semiconductor device is designed, in addition to a circuit pattern for realizing its essential operation of the semiconductor device, a plurality of characteristic measuring patterns for evaluating and confirming characteristics of various semiconductor elements disposed in the circuit pattern are disposed in the same chip.
FIG. 1
is a schematic view showing a characteristic measuring pattern in an existing semiconductor device. A characteristic measuring pattern including electrode pads
1101
to
1103
for inputting and outputting electric signals from and to measuring elements (not shown) to be measured is formed in a measuring pattern region
1100
. The shape of the measuring pattern region
1100
is rectangular, for example. The shape of the electrode pad
1101
is rectangular whose vertical side length is p and lateral side length is q. The shape of each of the electrode pads
1102
and
1103
is rectangular whose vertical side length is r and lateral side length is s. A distance t is provided between the electrode pad
1101
and the electrode pads
1102
,
1103
. Each of the electrode pads is disposed at a position away from a boundary of the measuring pattern region
1100
by a constant distance w. This is because the distance w is required between each of the electrode pads
1101
to
1103
for inputting and outputting electric signals to and from the measuring elements, and other electrode pads.
FIG. 2
is a schematic view showing an existing characteristic measuring pattern including four measuring pattern regions shown in FIG.
1
. There are provided a first measuring pattern region
1200
a
in which a first measuring element is disposed, a second measuring pattern region
1200
b
in which a second measuring element is disposed, a third measuring pattern region
1200
c
in which a third measuring element is disposed, and a fourth measuring pattern region
1200
d
in which a fourth measuring element is disposed, in a measuring pattern region
1200
. Each of the measuring pattern regions
1200
a
to
1200
d
has the same structure as that of the above-described measuring pattern region
1100
.
The first and second measuring pattern regions
1200
a
and
1200
b
have a mutually superposed region, the second and third measuring pattern regions
1200
b
and
1200
c
have a mutually superposed region, and the third and fourth measuring pattern regions
1200
c
and
1200
d
have a mutually superposed region. Each of distances between the electrode pads
1203
a
and
1202
b
, between the electrode pads
1203
b
and
1202
c
, and between the electrode pads
1203
c
and
1202
d
is w. The characteristic measuring pattern is constructed in this manner.
In the measuring pattern region
1200
shown in
FIG. 2
, if p=40 &mgr;m, q=40 &mgr;m, r=50 &mgr;m, s=40 &mgr;m, t=15 &mgr;m, and w=20 &mgr;m, the area is 78,300 &mgr;m
2
, and the chip size is extremely large.
When developing a new element, various measurement and evaluation are conducted and therefore, a TEG (Test Element Group) in which various evaluation elements are mounted and disposed is used. However, in the above-described existing semiconductor device, the number of elements that can be mounted per one chip when the TEG is used is limited.
Thereupon, there is disclosed a semiconductor device in which an electrode pad is shared by two adjacent measuring pattern regions (Japanese Patent Application Laid-open No. 4-361546 (published on Dec. 15, 1992)).
FIG. 3
is a schematic view showing a characteristic measuring pattern in a conventional semiconductor device disclosed in Japanese Patent Application Laid-open No. 4-361546 which is applied to four measuring elements. When the semiconductor device disclosed in Japanese Patent Application Laid-open No. 4-361546 is applied to four measuring elements, nine probe electrode pads
1301
to
1309
are provided.
There is provided a first measuring pattern region
1300
a
including electrode pads
1301
to
1303
in which a first measuring element is disposed. Similarly, there are provided a second measuring pattern region
1300
b
including electrode pads
1303
to
1305
in which a second measuring element is disposed, a third measuring pattern region
1300
c
including electrode pads
1305
to
1307
in which a third measuring element is disposed, and a fourth measuring pattern region
1300
d
including electrode pads
1307
to
1309
in which a fourth measuring element is disposed. That is, the electrode pads
1303
,
1305
,
1307
and
1309
are shared by two measuring pattern regions. The characteristic measuring pattern is constructed in this manner.
When an MOS (Metal Oxide Semiconductor) transistor is used as the measuring element, a gate of the first measuring element is connected to the electrode pad
1302
, a drain of the first measuring element is connected to the electrode pad
1301
, and a source of the first measuring element is connected to the electrode pad
1303
.
According to the disposing method disclosed in the Japanese Patent Application Laid-open No. 4-361546, a layout area of the characteristic measuring pattern is deleted as compared with a previous case in which the electrode pad is not shared by two patterns.
However, in recent years, the semiconductor devices are becoming larger scale and denser. This tendency increases the variety of elements constituting the semiconductor devices. Therefore, the number and kinds of the measuring element to be mounted on the same chip as the semiconductor element for evaluating the characteristics are increased. As a result, a region occupied by the characteristic measuring pattern, especially by its electrode pad is increased, and the chip is increased in size.
As a result, it becomes impossible to sufficiently suppress the increase of the chip size by the disposing method disclosed in the above-described Japanese Patent Application Laid-open No. 4-361546.
When the TEG is used, the number of measuring elements which are required to be mounted on one chip is largely increased, and a region occupied by their electrode pads is not sufficiently small. Thus, it is necessary to increase the chip size of the TEG, or to reduce the number of measuring elements to be mounted.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of reducing an area occupied by an electrode pad provided for evaluating the characteristics of a semiconductor element, and capable of effectively reducing an area of a characteristic measuring pattern in which the electrode pad is included.
According to one aspect of the present invention, a semiconductor device may be provided with a semiconductor substrate and five electrode pads disposed on the semiconductor substrate. Four of the electrode pads may form a rectangle, and the remaining one electrode pad may be disposed on the substantial center of the rectangle. The semiconductor device may be also provided with a plurality of semiconductor elements disposed between the electrode pads. The semiconductor elements may be connected to any of the five electrode pads and used for measuring characteristics.
A plurality of basic regions including five electrode pads disposed as same as the five electrode pads may be provided, and two of the electrode pads may be shared by two of the basic regions.
The semiconductor elements may be connected to the electrode pads located at vertexes of the rectangle.
The rectangle may be a regular square.
The semiconductor element may be a transistor. In this case, the transistor is preferably a field-effect transistor, and any one of a gate, a drain and a source of the field-effect transistor is preferably connected to the electrode
Clark Jhihan B
McGinn & Gibb, P.C.
NEC Corporation
Saadat Mahshid
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