Static information storage and retrieval – Read/write circuit – Testing
Patent
1985-05-28
1987-06-09
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Testing
365189, G11C 700
Patent
active
046725822
ABSTRACT:
A semiconductor device is provided which can be efficiently subjected to a function test at a high speed by write/read operations for each plurality of bits. The semiconductor device according to the present invention comprises an encoder for encoding a 1-bit signal to a signal of a plurality of bits and a decoder receiving a signal of a plurality of bits for decoding the same to a 1-bit signal in response to the states thereof, so as to simultaneously write each bit of the plurality of bits from the encoder in each corresponding memory cell of a plurality of simultaneously selected memory cells in a writing test mode, and to simultaneously read information signals stored in the plurality of simultaneously selected memory cells in a reading test mode thereby to decode the signals to a 1-bit signal corresponding to the plurality of information signals.
REFERENCES:
patent: 4464750 (1984-08-01), Tatematsu
patent: 4541090 (1985-09-01), Shiragasawa
"A Programmable 265K CMOS EPROM with On-Chip Test Circuits", by S. Tanaka et al, ISSCC 84/Thurs., Feb. 23, 1984.
Fujishima Kazuyasu
Kumanoya Masaki
Nishimura Yasumasa
Mitsubishi Denki & Kabushiki Kaisha
Popek Joseph A.
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