Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Patent
1998-03-12
2000-02-08
Butler, Dennis M.
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
713500, 713601, G06F 104, G06F 124
Patent
active
060237708
ABSTRACT:
A semiconductor device capable of solving problems involved in a conventional semiconductor device in that when a clock frequency is multiplied in the semiconductor device itself, the generation timing the an internal reset signal is shifted owing to supply voltage fluctuation of the like, and hence a plurality of test patterns must be prepared for respective test items when testing the semiconductor device. The present semiconductor device includes an internal clock halt circuit for suspending or passing a first internal clock signal to generate a second internal clock signal to be supplied to a signal synchronizing circuit in response to a signal applied to an external input terminal, and a data latch circuit for latching an external reset signal in response to the second internal clock signal output from the internal clock halt circuit, thereby controlling the interval at which the data latch circuit stops its latch operation.
REFERENCES:
patent: 5303390 (1994-04-01), Little
patent: 5359232 (1994-10-01), Eitrheim et al.
patent: 5552727 (1996-09-01), Nakao
Butler Dennis M.
Mitsubishi Denki & Kabushiki Kaisha
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