Semiconductor device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S030000, C324S750300

Reexamination Certificate

active

08069386

ABSTRACT:
A semiconductor device includes a CPU, a memory, a memory BIST circuit, a first selector that selects and outputs an address and control signal from the memory BIST circuit, when performing a test using the memory BIST circuit, and selects and outputs an address and control signal of the CPU when not performing a test using the memory BIST circuit, a second selector that selects and outputs write data from the memory BIST circuit when performing a test using the memory BIST circuit, and selects and outputs write data of the CPU when not performing a test using the memory BIST circuit, a first flip-flop that samples an output of the first selector (11) and a second flip-flop that samples an output of the second selector. An address and control signal and write data output from the first and second flip-flops are supplied to an address and control terminal and a write data terminal of the memory.

REFERENCES:
patent: 7146547 (2006-12-01), Fukatsu
patent: 7484141 (2009-01-01), Shikata
patent: 7707466 (2010-04-01), Gupta et al.
patent: 2003/0016578 (2003-01-01), Janik et al.
patent: 2004/0120181 (2004-06-01), Fukatsu
patent: 2004/0230395 (2004-11-01), Basto
patent: 2005/0193293 (2005-09-01), Shikata
patent: 2007/0204190 (2007-08-01), Hesse et al.
patent: 2008/0253208 (2008-10-01), Yamaguchi et al.
patent: 2006-155682 (2006-06-01), None
IEEE Journal of Solid-State Circuits, vol. 33, No. 11, Nov. 1998 1731 Processor-Based Built-In Self-Test for Embedded DRAM Jeffrey Dreibelbis, Member, IEEE, John Barth, Howard Kalter, Fellow, IEEE, and Rex Kho.

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