Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2009-12-22
2011-11-29
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C324S750300
Reexamination Certificate
active
08069386
ABSTRACT:
A semiconductor device includes a CPU, a memory, a memory BIST circuit, a first selector that selects and outputs an address and control signal from the memory BIST circuit, when performing a test using the memory BIST circuit, and selects and outputs an address and control signal of the CPU when not performing a test using the memory BIST circuit, a second selector that selects and outputs write data from the memory BIST circuit when performing a test using the memory BIST circuit, and selects and outputs write data of the CPU when not performing a test using the memory BIST circuit, a first flip-flop that samples an output of the first selector (11) and a second flip-flop that samples an output of the second selector. An address and control signal and write data output from the first and second flip-flops are supplied to an address and control terminal and a write data terminal of the memory.
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IEEE Journal of Solid-State Circuits, vol. 33, No. 11, Nov. 1998 1731 Processor-Based Built-In Self-Test for Embedded DRAM Jeffrey Dreibelbis, Member, IEEE, John Barth, Howard Kalter, Fellow, IEEE, and Rex Kho.
Foley & Lardner LLP
Gaffin Jeffrey A
Merant Guerrier
Renesas Electronics Corporation
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