Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-07-11
2010-11-02
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S025000, C714S700000, C714S716000, C714S718000, C714S724000, C714S815000, C714S707000, C714S719000, C716S030000, C716S030000, C716S030000, C365S201000, C324S535000, C324S764010
Reexamination Certificate
active
07827454
ABSTRACT:
An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.
REFERENCES:
patent: 6985547 (2006-01-01), Uht
patent: 2005-214732 (2005-08-01), None
Ernest, Dan et al., “Razor: Low-Power Pipeline Based on Circuit-Level Timing Speculation,” IEEE MICRO, 2004.
Gaffin Jeffrey A
McDermott Will & Emery LLP
Merant Guerrier
Renesas Electronics Corporation
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