Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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Details

C257SE33062

Reexamination Certificate

active

07348673

ABSTRACT:
A minute wiring structure portion including first wiring layers and first insulating layers, in which each of first wiring layers and each of first insulating layers are alternately laminated, is formed on a semiconductor substrate. A first huge wiring structure portion is formed on the minute wiring structure portion, and the first huge wiring structure portion is formed by successively forming on the minute wiring structure portion, in the following order, the first huge wiring portion including second wiring layers has a thickness of twice or more of the thickness of the first wiring layers and second insulating layers, in which each of second wiring layers and each of second wiring layers are alternately laminated, and a second huge wiring structure portion including third wiring layers has a thickness of twice or more of the thickness of the first wiring layer and a third insulating layer in which the elastic modulus at 25° C. is not more than that of the second insulating layers, each of the third wiring layers and each of the third insulating layers being alternately laminated.

REFERENCES:
patent: 2004/0164418 (2004-08-01), Sugiura et al.
patent: H11-074417 (1999-03-01), None
patent: H11-204560 (1999-07-01), None
patent: 11-219978 (1999-08-01), None
patent: 2000-150716 (2000-05-01), None
patent: 2000-323628 (2000-11-01), None
patent: 2003-204169 (2003-07-01), None
patent: 2003-338541 (2003-11-01), None
K. Kikuchi, et al., “A Package-process-oriented Multilevel 5-um-thick Cu Wiring Technology with Pulse Periodic Reverse Electroplating and Photosensitive Resin,” Proceeding of the IEEE 2003 International Interconnect Technology Conference (United States of America), Jun. 2003, p. 189-191.

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