Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2006-11-21
2006-11-21
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S780000, C257S782000, C257S784000, C257S666000
Reexamination Certificate
active
07138725
ABSTRACT:
In order to provide a downsized semiconductor device increased in function level with output terminals arranged along at least three sides of a semiconductor chip, the semiconductor device includes a semiconductor chip having a row of aggregated pads arranged on a main surface, and a row of output terminals arranged along at least three sides at a perimeter of the semiconductor chip, wire-bonded with the row of aggregated pads.
REFERENCES:
patent: 6258624 (2001-07-01), Corisis
patent: 6614101 (2003-09-01), Misumi et al.
patent: 6720666 (2004-04-01), Lim et al.
patent: 10-242373 (1998-09-01), None
patent: 2001-156107 (2001-06-01), None
patent: 2001-156237 (2001-06-01), None
Clark Jasmine
McDermott Will & Emery LLP
Renesas Technology Corp.
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