Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2005-04-26
2005-04-26
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S194000
Reexamination Certificate
active
06885593
ABSTRACT:
A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration. According to this invention, a pipelined dynamic memory (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory. This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.
REFERENCES:
patent: 4875160 (1989-10-01), Brown, III
patent: 4989182 (1991-01-01), Mochizuki et al.
patent: 5341341 (1994-08-01), Fukuzo
patent: 5511176 (1996-04-01), Tsuha
patent: 5761150 (1998-06-01), Yukutake et al.
patent: 5796669 (1998-08-01), Araki et al.
patent: 5901101 (1999-05-01), Suzuki et al.
patent: 5931951 (1999-08-01), Ando
patent: 5966724 (1999-10-01), Ryan
patent: 5999474 (1999-12-01), Leung et al.
patent: 6031782 (2000-02-01), Kobashi et al.
patent: 6094704 (2000-07-01), Martin et al.
patent: 6108244 (2000-08-01), Lee et al.
patent: 6130856 (2000-10-01), McLaury
patent: 6198689 (2001-03-01), Yamazaki et al.
patent: 6215714 (2001-04-01), Takemae et al.
patent: 6285626 (2001-09-01), Mizuno et al.
patent: 6469948 (2002-10-01), Mizuno et al.
patent: 6487135 (2002-11-01), Watanabe et al.
patent: 6647478 (2003-11-01), Tsuchida et al.
patent: 0 867 883 (1998-09-01), None
patent: 61-71494 (1986-04-01), None
patent: 11-353871 (1999-12-01), None
Itoh, Kiyoo, “Ultra LSI Memory”, (Baifukan, 1994), pp. 12-15, 86-87. 90-91, and 164-167.
Regitz et al. “A Three-Transistor-Cell, 1024-Bit, 500 NS MOS RAM”, IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 1970, pp. 42-43.
Kanno Yusuke
Mizuno Hiroyuki
Watanabe Takao
Miles & Stockbridge P.C.
Phan Trong
Renesas Technology Corp.
LandOfFree
Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3412441