Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Patent
1996-04-05
1998-04-14
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
257700, 257774, 257784, 361777, 361808, 361820, H01L 2348, H01L 2352
Patent
active
057395888
DESCRIPTION:
BRIEF SUMMARY
This application is filed under 35 U.S.C. 371, with priority of PCT/JP95/01622 filed Aug. 15, 1995.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device which exhibits high adherence strength at the corners of the IC chip so that there is no peel at the corners even though thermal strain is concentrated at the corners and in which a power supply terminal on an IC chip and a die pattern can be freely connected without forming the die pattern by extending corresponding to the position of the power supply terminal of the IC chip. This device can be utilized in various types of electronic apparatus.
2. Description of the Prior Art
In recent years, resin-sealed semiconductor devices with a large number of electrodes have been developed in concert with the high integration of the loading of IC chips. A typical example is a pin grid array (PGA). In the PGA an IC chip is mounted on one side of a circuit substrate and sealed in resin. A plurality of pins connected to the IC chip is arranged on the other side of the circuit substrate.
Although the PGA has an advantage that it is removably mounted on the mother board, there are problems associated with the PGA inasmuch as it is difficult to reduce the size because of existence of the pins.
Accordingly, a ball grid array (BGA) has been developed as a small semiconductor device sealed in resin in place of the PGA. The structure of a normal BGA will now be explained with reference to FIG. 7.
FIG. 7 is a sectional view of a conventional BGA.
This BGA is produced as follows. Using a cutting drill or the like, a plurality of through-holes 2 is formed in an almost-square resin substrate 1 formed of glass-epoxy resin or the like of a thickness of about 0.2 mm covered with laminated copper foil to a thickness of 18 .mu.m its top and bottom surfaces. Next, the surface of the substrate, including the wall surfaces of the through holes 2, is washed, after which a copper plated layer is formed by means of non-electrolytic plating and electrolytic plating on all surfaces of the resin substrate 1. At this time the copper plated layer is provided also at the inside of the through-holes 2.
Next, a laminate of plating resist (a resist used for areas not requiring plating) is provided and developed by exposure to light to form a pattern mask, after which the pattern is etched using CuCl.sub.2 +H.sub.2 O.sub.2, a common circuit substrate etching liquid.
A die pattern 3 of an IC chip and a connection electrode 4 for wire bonding are formed on the upper surface of the resin substrate 1 and a pad electrode 5 on which is formed a solder bump is provided on the lower surface. The connection electrode 4 and the pad electrode 5 are connected via the through-holes 2.
Next, an approximately 2 to 5 .mu.m nickel-plated layer is provided on the surface of the copper-plated layer of the electrode exposed on the upper and lower surfaces of the resin substrate 1. In addition, a gold-plated layer 31 of about 0.5 .mu.m, which affords superior characteristics for connection to the bonding wire, is provided on the nickel-plated layer.
A solder resist process is next performed on specified portions to form a resist film 6. An open section for the resist film which is a surface on which it is possible to solder a plurality of identical shapes in matrix form is formed on the lower surface of the resin substrate 1, whereby a circuit substrate 7 is completed.
Next, an IC chip 8 is secured directly to the gold-plated layer 31 of the die pattern 3 on the circuit substrate 7 using an adhesive (die bond material) 9. A power supply terminal and an I/O terminal of the IC chip 8 are connected to the connection electrode 4 using a bonding wire 10. Subsequently, the IC chip 8 and the bonding wire 10 are enclosed in resin in a transfer mold using a thermosetting resin 11 to protect the IC chip 8 from light.
In addition, solder balls are supplied to the pad electrode 5 formed on the lower surface of the resin substrate 1, and solder bumps 12 are formed by heatin
REFERENCES:
patent: 5285352 (1994-02-01), Pastore et al.
patent: 5397917 (1995-03-01), Ommen et al.
Ikeda Ienobu
Ishida Yoshihiro
Ohmori Yoshinobu
Terashima Kazuhiko
Toyoda Takeshi
Citizen Watch Co. Ltd.
Ostrowski David
Thomas Tom
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