Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-09-15
2004-03-16
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000, C714S036000
Reexamination Certificate
active
06708304
ABSTRACT:
TECHNICAL FIELD
This invention relates to a semiconductor device of the surface mount type having a boundary scanning function. More particularly, the invention relates to an electronic circuit device in which the semiconductor device is mounted on a wiring board, such as technology that can be effectively applied to a microcomputer or a microprocessor in which the external terminals that can be surface-mounted are arranged in the form of an array on the bottom surface of a CSP (chip-size package).
BACKGROUND OF THE INVENTION
The electronic circuits (hereinafter also simply referred to as boards) in which a semiconductor device is mounted on a circuit board have heretofore been tested by inputting and outputting data by bringing a probe into contact with a wiring on a circuit board among the semiconductor devices. As the mounting becomes highly dense in recent years, however, it is becoming difficult to bring the probe into contact with the wiring among the semiconductor devices. Instead of bringing the probe into contact with the wiring of the board, therefore, there has been put into practical use the boundary scanning technology according to which the semiconductor device is provided, in advance, with a constitution which makes access to the external terminals of the semiconductor devices through test terminals of the board.
The semiconductor device corresponding to the boundary scanning has flip-flops called boundary scanning cells attached to the external terminals thereof, and is provided with boundary scan-dedicated terminals such as TDI, TDO, TCK and TMS. Every boundary scanning cell is so connected as to work as a shift register that enters through TDI and goes out from TDO. TMS and TCK are control terminals of a test logic based on the boundary scanning. On the circuit board, TDI and TDO are connected among the semiconductor devices so that the boundary scanning cells are all connected as a shift register. By supplying a common control signal to TCK and TMS of all semiconductor devices that are mounted, it is allowed to move the long shift register to make access to all pins of all chips from the external side. This makes it possible to test the wiring board that is short-circuited or is opening, as well as to test whether the input/output circuit has been broken at the time of mounting.
The boundary scanning has been internationally standardized as IEEE Std 1149.1 in February, 1990.
The present inventors have studied about imparting the above function even to microcomputers that have not so far been furnished with the boundary scanning function. That is, when the external terminals such as of BGA (ball grid array) that can be surface-mounted are arranged in the form of an array on the bottom surface of the CSP, undesired stress may act on the connection portions of the wiring of the wiring board and the on external terminals causing them to be electrically separated. This, however, cannot be confirmed since the external terminals are positioned on the back surface of the CSP. To cope with this, therefore, it has been studied to use the boundary scanning function.
With the boundary scan-dedicated terminals such as TDI, TDO, TCK and TMS being added, however, it becomes no longer possible to guarantee the compatibility with the microcomputers of before being furnished with the boundary scanning function due to the number of the external terminals and the package size.
Even when it is attempted to newly furnish the debugging function, it is not allowed to newly provide external terminals for inputting and outputting debugging information from the standpoint of guaranteeing compatibility with the microcomputers of before being furnished with the above function.
This invention provides a semiconductor device capable of being furnished with the boundary scanning function without increasing the number of the external terminals.
This invention further provides a semiconductor device capable of being furnished with the debugging function without increasing the number of the external terminals.
The invention further provides an electronic circuit capable of easily confirming the defective connection between the wiring of the wiring board and the external terminals of the semiconductor device.
The above and other objects as well as novel features of the invention will become obvious from the following description of the specification and the accompanying drawings.
DISCLOSURE OF THE INVENTION
This invention is concerned with a semiconductor device comprising an internal circuit, a port circuit connected to the internal circuit, external terminals to which the port circuit is connected, and a boundary scanning circuit, wherein the boundary scanning circuit is the one that makes access to the external terminals through test access terminals, the test access terminals are also used as predetermined external terminals among the external terminals, selection means is provided for selectively determining whether the multi-use terminals be connected to the port circuit or to the boundary scanning circuit, the selection means selecting, as an initial state, the state where the multi-use terminals are connected to the boundary scanning circuit in response to the power-on reset.
Thus, the test access terminals need not be exclusively provided and, hence, the boundary scanning function can be furnished while guaranteeing pin compatibility of external terminals. If the boundary scanning function that is furnished is not utilized or if the port function of the multi-use terminals is not utilized despite the boundary scanning function is utilized, compatibility is completely guaranteed with the semiconductor device which has not been furnished with the boundary scanning function. The state where the multi-use terminals are connected to the boundary scanning circuit due to the power-on reset, is the initial state. It is therefore allowed to reliably verify the defective electric connection between the external terminals of the semiconductor device and the wiring board by utilizing the boundary scanning function. If the initial state cannot be accomplished, it becomes necessary to really operate the internal circuit (e.g., to have a CPU execute a program) to connect the multi-use terminals to the boundary scanning circuit. Here, however, when it is attempted to verify the defective electric connection between the external terminals and the circuit board, the normal operation of the internal circuit is not guaranteed if there is a defective connection and it is not possible to verify the defective electric connection by using the boundary scanning function.
The selection means may be so constituted as to initially determine the destination to which the multi-use terminals are to be connected according an external condition (e.g., logical value of mode signal) at the time of power-on reset. By taking into consideration the case where the semiconductor device is mounted on the circuit board that does not utilize the boundary scanning function, the device can be conveniently used if the multi-use terminals are connected, as the initial state, to the port circuit.
The state selected by the selection means can be changed by the CPU included in the internal circuit in compliance with an operation program.
According to a further concrete embodiment of the invention, the selection means includes a multiplexer which enables the multi-use terminals to be connected to the boundary scanning circuit or to the port circuit, and a port control register which initially sets, in response to the power-on reset, the control data for determining the state to be selected by the multiplexer. The state is selected by the multiplexer when the power-on is reset depending upon the state of the mode signal of when the power-on is reset.
The port control register may be constituted in a manner as described below in order to eliminate the misunderstanding caused by formal inconsistency that the control value of the multiplexer by the port control resister is not in agreement with the port control register access value by t
Kawasaki Ikuya
Noguchi Koki
Tsukimori Akifumi
Yoshioka Shin-ichi
Dildine R. Stephen
Miles & Stockbridge P.C.
Renesas Technology Corporation
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