Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-08-15
2004-01-13
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S763010, C324S765010
Reexamination Certificate
active
06678851
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates a semiconductor device and to an input terminal withstand voltage anomaly self-detection system which is built into the semiconductor device.
BACKGROUND OF THE INVENTION
A conventional withstand voltage anomaly test is carried out mostly before delivery of a target system to which a device is mounted. In this method, a withstand voltage anomaly does not occur in the test at the beginning, but in the case where deterioration of a terminal withstand voltage is caused due to aging after a user uses the device, this deterioration cannot be detected.
In addition, in another method, since a trigger is inputted from the outside of device into the target system so that the terminal withstand voltage is detected, the device cannot detect the anomaly by itself.
For instance, in a microcomputer, a reset input terminal is mostly brought into “Hi” level at the time of normal use for a long time, and its withstand voltage is deteriorated. Thus, even if a “Hi” level voltage is applied from the outside, an internal reset signal line cannot be brought into “Hi” level. In this case, the microcomputer is always in a reset state so that the reset cannot be released.
According to this invention, in the case where the withstand voltage anomaly gradually increases due to aging in the reset terminal and leakage current increases, the withstand voltage anomaly can be detected at a stage before the reset cannot be released, and a suitable post-process can be carried out.
Conventional arts are disclosed in (1) Japanese Patent Application Laid-Open No. 5-38039 (1993), (2) Japanese Patent Application Laid-Open No. 9-113564 (1997), (3) Japanese Patent Application Laid-Open No. 61-132882 (1986) and (4) Japanese Patent Application Laid-Open No. 10-14099 (1998).
In (1) Japanese Patent Application Laid-Open No. 5-38039 (1993), the conventional art relates to a latch-up overcurrent detection device. As this overcurrent detection device, a power source system, which is independent of an object to be detected; is used. When latch-up once occurs in a semiconductor device such as a CMOS chip, the chip cannot be generally expected to operate normally. Namely, when a device group in this conventional art is realized in one chip, and the latch-up once occurs, an A/D converter, a CPU and the like are not expected to operate normally.
On the contrary, an object of this invention is to detect a very small leakage current, not to detect overcurrent in a level of latch-up such that the chip cannot be expected to operate normally and one power source is used in one chip.
In (2) Japanese Patent Application Laid-Open No. 9-113564 (1997), there is described as “withstand voltage of a delay capacitor C is checked before a chip is packaged” on page 4, paragraph 0024. In this invention, the withstand voltage test is carried out by itself using the CPU in the chip after a user substrate is mounted. This conventional art is clearly different form the invention.
In (3) Japanese Patent Application Laid-Open No. 61-132882 (1986), an idea of the conventional art relates to an evaluation device, and this conventional art is basically different from the invention which carried out the withstand voltage test during actual use.
This conventional art describes that “a cause of deterioration of a gate insulating thin film withstand voltage of a semiconductor random access memory device due to aging is due to incomplete initial screening and products where deterioration of withstand voltage occurs due to aging cannot be sufficiently removed”. It is understood from this point that the object of this conventional art is not to carry out the withstand voltage test during actual use.
The withstand voltage test can be carried out while the device is being used actually in this invention. Therefore, this is advantageous because a malfunction which will be caused later can be prevented before it occurs. This conventional art is different from the invention.
In (4) Japanese Patent Application Laid-Open No. 10-14099 (1998), an object of this conventional art is “to provide an overcurrent detection circuit which is capable of setting an arbitrary overcurrent detection value and of reducing the effect of dispersion of characteristics in production”. This conventional art is different from the invention where its object is not to reduce the effect of dispersion of characteristics in production.
In addition, this publication describes that “an arbitrary overcurrent detection value can be set”. However, this means that a set value at the time of design is arbitrary, and this set value cannot be changed after fabrication. The invention has an advantage that a set value can be changed even after the fabrication of the device.
Further, in the method of this conventional art, a leakage current caused by deterioration of a gate oxide film portion of an MOS transistor cannot be detected. In the invention, as detailed later, a leakage in a gate oxide film can be detected.
According to these points, this conventional art is different from the invention.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device detecting an input terminal withstand voltage anomaly or a leakage current anomaly by means of the device itself.
According to one aspect of this invention, a semiconductor device comprises a program storage unit and an A/D converter which converts an analog signal inputted from an A/D conversion input terminal into a digital signal. The semiconductor device further comprises a withstand voltage anomaly test terminal. A selection unit is actuated by a program in the program storage unit and selects the A/D conversion input terminal at the time of normal operation and selects the withstand voltage anomaly test terminal at the time of test operation. A potential signal of the withstand voltage anomaly test terminal at the time of test operation is detected as a digital value by the A/D converter based on the program in the program storage unit. A central processing unit compares the detected digital value with the judgment reference value stored in the data storage unit and judges the quality of said semiconductor device based on the result of comparison. Therefore, the semiconductor device can detect an input terminal withstand voltage anomaly or a leak current anomaly by using the built-in A/D converter.
According to another aspect of this invention, a semiconductor device comprises a program storage unit, a data storage unit and an A/D converter which converts an analog signal inputted from an A/D conversion input terminal into a digital signal. The semiconductor device further comprises a withstand voltage anomaly test terminal which is pulled up from the outside. A selection unit composed of an A/D input selector circuit is actuated by a program in the program storage unit and selects the A/D conversion input terminal at the time of normal operation and selects the withstand voltage anomaly test terminal at the time of test operation. A potential signal of the withstand voltage anomaly test terminal at the time of test operation is detected as a digital value by the A/D converter based on the program in the program storage unit and the digital value is compared with a judgment reference value set in the data storage unit so that a judgment is made as to normality or anomaly. Therefore, the semiconductor device can detect an input terminal withstand voltage anomaly or a leak current anomaly by using the built-in A/D converter.
According to still another aspect of this invention, a semiconductor device comprises a program storage unit, a data storage unit and an A/D converter which converts an analog signal inputted from an A/D conversion input terminal into a digital signal. A withstand voltage anomaly test terminal is pulled down from the outside. A selection unit composed of an A/D input selector circuit is actuated by a program in the program storage unit and selects the A/D conversion input terminal at the time of normal operation and selects the withstand v
Britt Cynthia
De'cady Albert
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
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