Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2002-03-07
2004-04-27
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S723000
Reexamination Certificate
active
06727583
ABSTRACT:
BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT
The present invention relates to a semiconductor device, particularly to a multi-chips module (MCM) type semiconductor device adapted to be mounted on a board and to be electrically connected to the board.
JP-A-11-220077 discloses that a coefficient of thermal expansion and so forth is adjusted to restrain a crack of a semiconductor element and/or an under-fill in a flip-chip type semiconductor device. JP-A-2000-40775 discloses a shape of an oblique surface of the under-fill is adjusted to restrain the crack of the semiconductor element.
OBJECT AND SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device in which an excessive stress, for example, an excessive thermal stress is restrained to maintain a reliability of the semiconductor device.
In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.
Since the thickness of the each of the semiconductor electric chips in the direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than the thickness of the substrate in the direction, a bending rigidity of the each of the semiconductor electric chips is kept small while a bending rigidity of the substrate is kept great. Therefore, a stress in and on the each of the semiconductor electric chips is kept small when the semiconductor device is bent with a thermal deformation thereof and/or an external force applied to the semiconductor device.
When a Young's modulus of the semiconductor electric chips is larger than a Young's modulus of the substrate, it is more important that the bending rigidity of the each of the semiconductor electric chips is kept small, because, the greater the Young's modulus of the semiconductor electric chips is, the greater the stress in and on the each of the semiconductor electric chips is. When a linear expansion coefficient of the semiconductor electric chips is smaller than a linear expansion coefficient of the substrate, it is more important that the bending rigidity of the each of the semiconductor electric chips is kept small. The semiconductor electric chips may be distant away from each other in a direction perpendicular to the direction.
The semiconductor device may further comprise a synthetic resin layer connected to the each of the semiconductor electric chips and the substrate so that the each of the semiconductor electric chips is connected to the substrate through the synthetic resin layer. When the Young's modulus of the semiconductor electric chips is larger than a Young's modulus of the synthetic resin layer, it is more important that the bending rigidity of the each of the semiconductor electric chips is kept small, because, the greater the Young's modulus of the semiconductor electric chips is, the greater the stress in and on the each of the semiconductor electric chips is. When the linear expansion coefficient of the semiconductor electric chips is smaller than a linear expansion coefficient of the synthetic resin layer, it is more important that the bending rigidity of the each of the semiconductor electric chips is kept small. When the semiconductor device further comprises an electrically conductive member through which the each of the semiconductor electric chips is electrically connected to the substrate, it is preferable for reinforcing effectively the electrically conductive member that the electrically conductive member is surrounded by the synthetic resin layer. When the semiconductor device further comprises the electrically conductive member through which the each of the semiconductor electric chips is electrically connected to the substrate, and an electrically insulating layer including synthetic resin arranged between the synthetic resin layer and the semiconductor electric chips so that the synthetic resin layer is connected to the semiconductor electric chips through the electrically insulating layer and including a surface extending perpendicular to the direction, it is preferable for restraining the excessive stress on the electrically conductive member when the semiconductor device is bent that the electrically conductive member extends on the surface between the electrically insulating layer and the synthetic resin layer. It is preferable that a Young's modulus of the synthetic resin layer under DMA measuring is not more than 10 GPA, and a linear expansion coefficient of the synthetic resin layer under TMA measuring is not more than 35×10
−6
K
−1
.
When the semiconductor device further comprises a metallic member connected to the semiconductor electric chips, and an adhesive through which the metallic member connected to the semiconductor electric chips, it is preferable for restraining the excessive stress on the semiconductor electric chips that a Young's modulus of the adhesive is smaller than a Young's modulus of the semiconductor electric chips.
When the each of the semiconductor electric chips includes a first surface facing to the substrate and a second surface as a reverse surface with respect to the first surface, it is preferable for restraining a crack on the semiconductor electric chips that the second surface of at least one of the semiconductor electric chips is a grinder-finished surface, because a maximum principal stress is generated on the second surface when the semiconductor device is bent by the internal thermal deformation or the external force.
The thickness of the each of the semiconductor electric chips may be not more than 50% of the thickness of the substrate. It is more preferable that the thickness of the each of the semiconductor electric chips is not more than 30% of the thickness of the substrate. It is preferable that 12<As (×10−6K−1)≦20 and tc/ts≦−−0.04As+1.1 when a linear expansion coefficient of the substrate under TMA measuring is As, and a thickness of the each of the semiconductor chips is tc and a thickness of the substrate is ts.
It is proved on the basis of theoretical calculations as follows that the present invention is effective in various cases. A thermal stress on and in the semiconductor electric chip in a temperature variation range between −55° C. and 125° C. was calculated by two-dimensional elasticity analysis of finite element method.
FIG. 2
shows a model of a semiconductor device to be analyzed. Principal stresses at a point A (central position of reverse surface of semiconductor chip) and at a point B (upper end of oblique surface of under fill joining surface of semiconductor chip) are calculated as important values by which whether or not a crack occurs in the semiconductor device is judged. A size of finite element of the semiconductor electric chip is set at 0.1 mm×0.05 mm for the calculation, because the point B is a stress concentration point at which the stress has a singularity.
As shown in
FIG. 3
showing a calculation result, the principal stresses at the point A and B do not changed significantly in accordance with a number of the semiconductor electric chips on the substrate and/or a distance between the semiconductor electric chips. As shown in
FIG. 4
showing a calculation result, the principal stresses at the point A and B do not changed significantly in accordance with a width of the semiconductor electric chip. As shown in
FIG. 5
showing a calculation result,
Imasu Satoshi
Naito Takahiro
Naka Yasuhiro
Tanaka Naotaka
Yoshida Ikuo
Clark Sheila V.
Townsend and Townsend / and Crew LLP
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