Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-12-09
2003-02-04
DeCady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C326S016000
Reexamination Certificate
active
06516431
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device comprising a switch such as a redundancy circuit for relieving a random access memory (RAM) of its failures.
DESCRIPTION OF THE BACKGROUND ART
FIG. 47
is a circuit diagram of a conventional semiconductor device. The conventional semiconductor device comprises a 5-bit word mode RAM
100
, a scan path circuit
210
a
, a failure relief circuit
220
a
, and a logic circuit
300
. The RAM
100
and the logic circuit
300
exchange data therebetween through the failure relief circuit
220
a
. A detailed description of the scan path circuit
210
a
and the failure relief circuit
220
a
is given for example in Japanese Patent Laid-open No. P08-94718A.
The scan path circuit
210
a
receives and holds 5-bit data transmitted over lines L
1
through L
5
, rewrites 5-bit data therein on the basis of serial data SS
1
from a line L
19
, and outputs 5-bit data therein as serial data SS
2
to a line L
20
. The scan path circuit
210
a
also outputs 4 bits of 5-bit data therein in parallel form as 1-bit data G
1
through G
4
.
Whether or not there is an error in the data transmitted over the lines L
1
through L
5
can be checked by looking up the serial data SS
2
from the scan path circuit
210
a
, so the RAM
100
can be tested for failure.
The scan path circuit
210
a
and the failure relief circuit
220
a
serve as a redundancy circuit for relieving the RAM
100
of its failures. For example, if there is an error in the third bit of the RAM
100
, the serial data SS
1
on the line L
19
is set properly so that the 1-bit data G
1
through G
4
are set to “1”, “1”, “0”, “1”, respectively. This provides connections between the lines L
11
and L
1
, between the lines L
12
and L
2
, between the lines L
13
and L
4
, and between the lines L
14
and L
5
, except the line L
3
of trouble. Similarly, connections are made between lines L
15
and L
6
, between a line L
16
and lines L
7
, L
8
, between lines L
17
and L
9
, and between lines L
18
and L
10
. Thus, even if the RAM
100
contains such a failure bit, it can be used as a trouble-free 4-bit word mode RAM, when viewed from the logic circuit
300
, by making connections between the lines L
1
through L
10
, except a trouble line, and the lines L
11
through L
18
.
However, since the lines L
11
through L
14
are connected to four lines selected from among the five lines L
1
through L
5
according to data on the lines L
1
through L
5
and on the line L
19
, and since the data on the lines L
1
through L
5
may not be correct due to a failure in the RAM
100
, it would be considerably difficult for the failure relief circuit
220
a
to determine which of the lines L
11
through L
14
each data on the lines L
1
through L
5
is transmitted to.
The above problem offers a considerable difficulty in testing the logic circuit
300
. For example, a predetermined expected value is stored into the RAM
100
at every address and applied to the logic circuit
300
through the failure relief circuit
220
a
. This enables the test of whether the logic circuit
300
operates as intended or not. In such a test, which of the lines L
11
through L
14
each expected value on the lines L
1
through L
5
is transmitted to has to be determined from the expected value itself. However, if a failure occurs in the RAM
100
, this determination becomes hard to be made, and thus, a serious difficulty arises in the test of the logic circuit
300
.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a semiconductor device comprising: a memory circuit outputting N-bit data (N≧2) in parallel form; a switch including a data holding circuit having a scan path circuit receiving and holding the N-bit data from the memory circuit, the switch receiving a switch control signal and selecting and outputting M-bit data (M<N) from the N-bit data of the memory circuit, the M-bit data outputted from the switch being predetermined M-bit data out of the N-bit data from the memory circuit if the switch control signal satisfies a predetermined condition, and being M-bit data determined according to data held in the data holding circuit if the switch control signal does not satisfy the predetermined condition; and a logic circuit to be tested, receiving the M-bit data outputted from the switch.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, the switch selects and outputs M-bit data directly outputted from the memory circuit.
According to a third aspect of the present invention, in the semiconductor device of the first aspect, the switch selects and outputs M-bit data in the scan path circuit from the memory circuit.
According to a fourth aspect of the present invention, in the semiconductor device of the first aspect, the switch further includes a selector block for selecting and outputting M-bit data from the memory circuit if the switch control signal satisfies the predetermined condition and for selecting and outputting M-bit data from the scan path circuit if the switch control signal does not satisfy the predetermined condition.
According to a fifth aspect of the present invention, in the semiconductor device of the first aspect, the data holding circuit further includes a register for holding data outputted from the scan path circuit.
According to a sixth aspect of the present invention, in the semiconductor device of the fifth aspect, if the switch control signal satisfies the predetermined condition, the register resets data held therein with a predetermined value.
According to a seventh aspect of the present invention, in the semiconductor device of the first aspect, the scan path circuit includes a plurality of series-connected scan path blocks, each of the plurality of scan path blocks having a comparator and receiving 1-bit data from expected data and resetting data held therein with a predetermined value according to a comparison result between the 1-bit data from the expected data and the 1-bit data from the memory circuit.
According to an eighth aspect of the present invention, in the semiconductor device of the first aspect, each of the plurality of scan path blocks resets data held therein with another predetermined value, if the switch control signal satisfies the predetermined condition.
According to a ninth aspect of the present invention, in the semiconductor device of the seventh aspect, each of the plurality of scan path blocks includes a selector for selecting either 1-bit data held therein or serial data from an ante-stage scan path block and for outputting the selected data to a post-stage scan path block.
According to a tenth aspect of the present invention, in the semiconductor device of the seventh aspect, the data holding circuit further includes a register for holding data outputted from the scan path circuit; each of the plurality of scan path blocks changes the comparison result into a predetermined value according to 1-bit data from the register.
In accordance with the first aspect, if the switch control signal satisfies a predetermined condition, the switch selects and outputs predetermined M-bit data out of the N-bit data from the memory circuit. This eliminates the need for determining a signal transmission path to which the data is transmitted according to the data held in the data holding circuit, thus facilitating a test of the logic circuit using the scan path circuit and the memory circuit.
In accordance with the second aspect, the logic circuit can be tested using the M-bit data outputted from the memory circuit.
In accordance with the third aspect, the logic circuit can be tested using the data outputted from the scan path circuit.
In accordance with the fourth aspect, the switch can be composed of the data holding circuit and the selector blocks.
In accordance with the fifth aspect, if the switch control signal does not satisfy a predetermined condition, the switch selects and outputs data corresponding to the data held in the register independently of the data held
DeCady Albert
Dooley Matthew
Mitsubishi Denki & Kabushiki Kaisha
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