Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-08-21
2002-11-05
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S288000, C438S015000
Reexamination Certificate
active
06476414
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more specifically to a semiconductor device capable of precisely estimating a gate length of a MOS transistor.
In the prior art, the gate length of a MOS transistor is measured in the process of a semiconductor device fabrication, by preparing a monitor pattern (check transistor) on a wafer and by physically measuring the gate length L of the check transistor by use of a length measuring SEM (scanning electron microscope).
However, the above mentioned measuring method can no longer ensure a satisfactory precision of the length measurement because of a recent tendency of shortening of the gate length for the microminiaturization of the semiconductor device. In addition, since the above mentioned measuring method is a localized measurement, an error on the order of ±0.01 &mgr;m will occur because of the influence of a gate shape and dependently upon the manner of measurement, with the result that it is impossible to grasp a precise gate length.
Furthermore, the above mentioned measuring method is convenient in checking a difference between patterns. However, since the above mentioned measuring method is carried out in the process of the semiconductor device fabrication, when it is desired to carry out a number of measurements such as a full-chip measurement and a full-number measurement, it is unsuitable because it is needs time and because there is a high degree of possibility that dust is deposited on the wafer.
Under this circumstance, another gate length measuring method as shown in
FIG. 1
may be considered by persons skilled in the art although it is not well known. This gate length measuring method is intended to an electrical characteristics in order to realize a measurement precision higher than that obtained in the above mentioned physical measurement of the size.
In the gate length measuring method as shown in
FIG. 1
, a gate voltage Vg of a single MOS transistor
12
when a predetermined current Io starts to flow through the MOS transistor
12
is considered to be a threshold voltage Vt (Vg=Vt). As shown by a plotted line
11
in
FIG. 3
, a gate voltage-gate length (Vt-L) characteristics Vt(
1
) is prepared by measuring the threshold voltage Vt of various MOS transistors which were formed under the same fabricating condition to have different predetermined gate lengths. In
FIG. 3
, the axis of abscissas Lpoly indicates the gate length in terms of micrometer, and the threshold voltage Vt is indicated by the axis of ordinates at a left side in terms of volt.
Thus, the gate voltage Vg of the MOS transistor
12
shown in
FIG. 1
when a predetermined current Io (for example, 1 &mgr;A) starts to flow through the MOS transistor
12
is measured as the threshold voltage Vt, and a gate length of the MOS transistor
12
is estimated from the measured gate voltage Vt and the previously prepared Vt-L characteristics Vt(
1
) as shown in FIG.
3
.
In the gate length measuring method shown in
FIG. 1
, however, the measured gate voltage Vt of the MOS transistor
12
does not necessarily correspond to the actual gate length L of the MOS transistor
12
, because an estimated gate length is deviated from the actual gate length L when the Vt-L characteristics Vt(
1
) was shifted to a distinct Vt-L characteristics Vt(
2
) as designated by the reference number
10
in
FIG. 3
because of unintentional causes such as unpreferable remaining charges.
The reason for this will be described briefly. The gate voltage (threshold voltage) Vt, which is one fundamental characteristics of the MOS transistor, is influenced by not only the gate length L but also the other factors including the thickness of a gate oxide film, the surface concentration of a silicon substrate, the existence of electric charges at a boundary between the gate oxide film and the silicon substrate, the existence of electric charges within the gate oxide film, etc.
Since the degree of influence to the gate voltage (threshold voltage) Vt, of variation of the electric charges existing within the gate oxide film and at the boundary between the gate oxide film and the silicon substrate, was small hitherto, it was considered that if the precision of the gate oxide film thickness and the substrate surface concentration was elevated in the fabricating process, it is possible to presume the gate length L from the gate voltage (threshold voltage) Vt.
Recently, however, the value of the gate voltage (threshold voltage) Vt has become small, with the result that it has become unallowable to ignore the shift of the gate voltage (threshold voltage) Vt, caused by factors such as the electric charges existing within the gate oxide film and at the boundary between the gate oxide film and the silicon substrate, other than the gate oxide film thickness and the substrate surface concentration.
Since the variation of the above mentioned electric charges occurs in various situations in the process of the semiconductor device fabrication, it is difficult to control the electric charges in question, differently from the gate oxide film thickness and the substrate surface concentration. Therefore, it is unavoidable that the gate voltage (threshold voltage) Vt is often shifted because of the influence of the uncontrollable remaining electric charges.
Therefore, although the gate voltage (threshold voltage) Vt was shifted by the uncontrollable remaining electric charges to assume the Vt-L characteristics Vt(
1
) shown in
FIG. 3
, if the gate length is estimated by applying the measured gate voltage Vt to the Vt-L characteristics Vt(
2
) which was obtained by measuring the gate voltage (threshold voltage) Vt of various MOS transistors which were formed under the same fabricating condition to have the same gate oxide film thickness and the same substrate surface concentration but to have different gate lengths, the estimated gate length is resultantly deviated from the actual gate length L.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device capable of precisely estimating a gate length of a MOS transistor, without being influenced by the uncontrollable remaining electric charges.
The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor device having a checking pattern composed of a combination of MOS transistors having different gate lengths so that a threshold voltage difference can be measured.
According to the present invention, there is provided a semiconductor device having a checking pattern composed of a combination of MOS transistors having different gate lengths so that a threshold voltage difference between the MOS transistors can be measured by flowing a current through the MOS transistors.
As seen from the above, in order to obtain the gate length of the MOS transistor, according to the present invention, the physical measurement of a gate length is not executed in the process of a semiconductor device fabrication, nor is the estimation carried out on the basis of the electrical characteristics (threshold voltage Vt) obtained from the electrical measurement of a single MOS transistor. According to the present invention, the gate length of the MOS transistor can be precisely estimated on the basis of a threshold voltage difference (dVt) between two MOS transistors having different gate lengths, which were formed in the same semiconductor device fabricating process and which are combined to form the checking pattern.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.
REFERENCES:
patent: 5359296 (1994-10-01), Brooks et al.
patent: 5796767 (1998-08-01), Aizawa
patent: 5966005 (1999-10-01), Fujimori
patent: 9-251059 (1997-09-01), None
McGinn & Gibb PLLC
NEC Corporation
Nguyen Dilinh
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