Semiconductor device

Details Semiconductor device Semiconductor device

2000-08-28

2002-09-17

Talbott, David L. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

On insulating carrier other than a printed circuit board

C257S747000, C257S748000, C257S762000, C257S778000, C257S780000

Reexamination Certificate

active

06452256

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having external terminals on its semiconductor chip.
As equipment incorporating semiconductor devices are becoming smaller in size and weight as a result of widespread use of mobile communication terminals in recent years, there are growing demands for semiconductor devices that can cope with the trend for miniaturization.
Technologies are available that attempt to reduce the size of the semiconductor device as close to the chip size as possible. A package of such a semiconductor device is generally called a CSP (chip size package or chip scale package).
A conventional process of making CSPs involves slicing the wafer into individual chips and packaging each of these chips separately. A wafer-level CSP technology has been under development which forms a rewiring layer and external terminals on chips still in the form of a wafer and finally cutting the wafer into individual chips to reduce the packaging cost. An example of the wafer-level CSP technology has been proposed in an article in the Nikkei Microdevice, April 1998 issue (pages 164-167), “Method of fabricating CSP, one of the prospective candidates for chip-size packaging, at low cost is developed.”
SUMMARY OF THE INVENTION
In the conventional technology described above, however, when a volume occupation factor of a rewiring layer in a projected plane of the semiconductor chip's principal surface is increased, it has been found that the semiconductor IC chips or wafer may warp and delamination may occur between layers.
The extensive examination into this problem by the inventor of this invention has provided the following findings. In the above CSP, the rewiring layer is arranged in the projection plane of the semiconductor chip's principal surface. The rewiring layer uses such metals as Cu. Because general metal materials including Cu have larger coefficients of linear expansion than that of the semiconductor chip, thermal load (temperature change) applied to the semiconductor device during manufacture or during the use of the product produces a difference in thermal deformation between the semiconductor chip and the rewiring layer, producing thermal stresses in the interior of the rewiring layer. When the rewiring layer has large thermal stresses, the semiconductor chip as a whole warps posing problems to such processes following the formation of the rewiring layer as the patterning of a protective film, the forming of external terminals, and the mounting the chip on a substrate. Further, a high stress that occurs in an interface between the rewiring layer and an interlayer insulation film or a protective film may result in delamination of these layers. These problems become conspicuous as the level of integration of the semiconductor device goes up and the volume occupation factor of the rewiring layer in the projected plane of the semiconductor chip becomes higher. In the semiconductor devices that make provisions for an increased speed, an area in the projected plane of the semiconductor chip's principal surface where there is no rewiring layer can be filled with power and ground wires to reduce electromagnetic noise. This, however, further increases the volume occupation factor.
In the wafer-level CSP described above, because the rewiring layer is formed while the chips are still in the form of a wafer, the wafer easily warps, making the problem more serious than when the packaging is done on single chips.
The object of this invention is to solve at least one of the above-described problems and provide a semiconductor device in which the semiconductor chips or wafer do not warp easily and delamination does not occur easily at an interface of an interlayer insulation film.
The semiconductor device to achieve the above objective comprises, for example: a semiconductor chip; electrode pads formed on the semiconductor chip; a first protective film covering an electrode pad forming surface of the semiconductor chip; an insulating film formed over the first protective film; lands formed over the insulating film and made mainly of a Cu
2
O—Cu composite alloy (with a largest Cu
2
O content); wiring line electrically connecting the electrode pads and the lands and made mainly of a Cu
2
O—Cu composite alloy; a second protective film formed over the insulating film to expose at least a part of the surface of the lands; and external terminals joined to the lands.
With this arrangement, because the Cu—Cu
2
O composite alloy has a smaller linear thermal expansion coefficient and a smaller elastic modulus than those of pure copper, the difference in the linear thermal expansion coefficient between the silicon oxide layer mainly used as the insulating film in the semiconductor chip wiring structure and the rewiring layer becomes smaller, thus reducing thermal stresses in the rewiring layer. This in turn reduces the warping of the semiconductors chips or a wafer and prevents delamination between the rewiring layer and the interlayer insulating film or protective film.


REFERENCES:
patent: 5280850 (1994-01-01), Horiguchi et al.
patent: 5960308 (1999-09-01), Akagawa et al.
patent: 1154649 (1999-02-01), None
patent: 11204560 (1999-07-01), None
“Method of Fabricating CSP, one of the prospective candidates for chip-size packaging at low cost is developed” (Nikkel Microdevice, Apr. 1998 Issue pp. 164-167).

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