Semiconductor container structure with diffusion barrier

Details Semiconductor container structure with diffusion barrier Semiconductor container structure with diffusion barrier

2002-10-09

2004-08-24

Thomas, Tom (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S250000, C438S393000

Reexamination Certificate

active

06780706

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to development of semiconductor container structures, and in particular to development of semiconductor container capacitor structures having a diffusion barrier, and apparatus making use of such container capacitor structures.
BACKGROUND
Many electronic systems include a memory device, such as a Dynamic Random Access Memory (DRAM), to store data. A typical DRAM includes an array of memory cells. Each memory cell includes a capacitor that stores the data in the cell and a transistor that controls access to the data. The capacitor typically includes two conductive plates separated by a dielectric layer. The charge stored across the capacitor is representative of a data bit and can be either a high voltage or a low voltage. Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as digit lines, which are coupled to input/output (I/O) lines through transistors used as switching devices. Typically, for each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line. However, each such memory cell is coupled to, or associated with, only one digit line of a digit line pair through an access transistor.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines, and memory cells are associated with the intersections of the lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a word line or row decoder and to a digit line or column decoder. The row decoder activates a word line in response to the word line address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The column decoder selects a digit line pair in response to the digit line address. For a read operation, the selected word line activates the access transistors for a given word line address, the charge of the selected memory cells are shared with their associated digit lines, and data is sensed and latched to the digit line pairs.
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing memory cell area and its accompanying capacitor area, since capacitance is generally a function of plate area. Additionally, there is a continuing goal to further decrease memory cell area.
A principal method of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. One common form of stacked capacitor structure is a cylindrical container stacked capacitor, with a container structure forming the bottom plate of the capacitor. Such container structures may have shapes differing from a substantially cylindrical form, such as an oval or other three-dimensional container. The container structures may further incorporate fins.
Another method of increasing cell capacitance is through the use of high dielectric constant material in the dielectric layer of the capacitor. In order to achieve the charge storage efficiency generally needed in 256 megabit(Mb) memories and above, materials having a high dielectric constant, and typically dielectric constants greater than 50, can be used in the dielectric layer between the bottom plate and the top plate of the capacitor. The dielectric constant is a characteristic value of a material and is generally defined as the ratio of the amount of charge that can be stored in the material when it is interposed between two electrodes relative to the charge that can be stored when the two electrodes are separated by a vacuum.
Unfortunately, high dielectric constant materials are often incompatible with existing processes. This incompatibility is a result of the oxygen-containing ambient often present during the deposition of high dielectric constant materials or during subsequent annealing steps.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved container structure and methods of producing same.
SUMMARY
In one embodiment, the invention includes a semiconductor container structure. The semiconductor container structure includes a bottom conductive layer having a closed bottom portion and sidewall portions extending upward from the bottom portion, a diffusion barrier layer overlying at least the bottom portion of the bottom conductive layer, and a dielectric layer overlying the diffusion barrier layer and the bottom conductive layer. In a further embodiment, the dielectric layer contains at least one metal oxide material. The diffusion barrier layer acts to inhibit atomic diffusion to at least a portion of the bottom conductive layer. In another embodiment, the diffusion barrier layer contains one or more refractory metal nitride, silicon oxide, silicon nitride or silicon oxynitride materials. In a further embodiment, the bottom conductive layer includes a primary conductive layer overlying a conductive barrier layer. In a still further embodiment, the conductive barrier layer comprises a metal nitride. In another embodiment, the primary conductive layer contains a metal layer, a metal alloy layer or a conductive metal oxide layer. In a further embodiment, the primary conductive layer contains one or more metals of the refractory metals, the platinum metals group and the noble metals group. The one or more metals may be in the form of the metal, a metal alloy or a conductive metal oxide. In yet another embodiment, the diffusion barrier layer is adjacent the bottom portion of the bottom conductive layer, and the dielectric layer is adjacent the sidewall portions of the bottom conductive layer. In a still further embodiment, the dielectric layer contains one or more Ba
x
Sr
(1-x)
TiO
3
, BaTiO
3
, SrTiO
3
, PbTiO
3
, Pb(Zr,Ti)O
3
, (Pb,La)(Zr,Ti)O
3
, (Pb,La)TiO
3
, Ta
2
O
5
, KNO
3
or LiNbO
3
dielectric materials.
In another embodiment, the invention includes a semiconductor container structure. The semiconductor container structure includes a bottom conductive layer having a closed bottom portion and sidewall portions extending upward from the bottom portion, and a diffusion barrier layer overlying at least the bottom portion of the bottom conductive layer and exposing a remaining portion of the bottom conductive layer. The semiconductor container structure further includes a dielectric layer overlying the diffusion barrier layer and the bottom conductive layer, wherein the dielectric layer is adjacent the remaining portion of the bottom conductive layer.
In a further embodiment, the invention includes a semiconductor container structure. The semiconductor container structure includes a bottom conductive layer comprising a metal layer and having a closed bottom portion and sidewall portions extending upward from the bottom portion and a diffusion barrier layer overlying at least the bottom portion of the bottom conductive layer. The diffusion barrier layer contains at least one of silicon oxide, silicon nitride, silicon oxynitride and refractory metal nitride materials. The semiconductor container structure further includes a dielectric layer overlying the diffusion barrier layer and the bottom conductive layer.
In a further embodiment, the invention includes a method of forming a semiconductor structure. The method includes forming an insulating layer on a substrate and forming an opening in the insulating layer. The opening has a bottom portion overlying an exposed portion of the substrate and sidewall portions defined by the insulating layer. The method

Affiliated with

Also associated with

Rating

Semiconductor container structure with diffusion barrier does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor container structure with diffusion barrier, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor container structure with diffusion barrier will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3270537