Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-22
2002-06-04
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S404000, C438S427000, C438S436000
Reexamination Certificate
active
06399449
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit (IC) wherein devices are segregated using trench isolation techniques, and more specifically to a semiconductor device wherein a deep trench is formed in a shallow trench. Still more specifically, the present invention relates to a method of fabricating a trench isolator wherein a deep trench is provided in a shallow trench.
2. Description of the Related Art
BIMOS (or BiCMOS) is a technology that integrates both MOS (metal-oxide-semiconductor) and bipolar device structures on the same chip, and thus offering the benefits of both MOS and bipolar circuits. It is known in that art that shallow and deep trenches are respectively used to isolate MOS and bipolar devices. Each of deep trenches is formed in a shallow trench in order to meet a current tendency of achieving higher packaging of device.
Before turning to the present invention it is deemed advantageous to briefly describe, with reference to
FIGS. 1A-1D
and
2
, a conventional technique of trench isolation using shallow and deep trenches for segregating active regions. This conventional technique is disclosed in Japanese Laid-open Patent Application No 5-315439.
FIGS. 1A-1D
are diagrams showing a series of fabrication processes of shallow and deep trenches, which are used to respectively isolate CMOS and bipolar devices (not shown). It is to be noted that each of
FIGS. 1A-1D
shows only three shallow trenches (one is shown in part)
10
a
-
10
c
and only one deep trench
14
are illustrated for the sake of simplifying the illustration.
Referring to
FIG. 1A
, the process begins with a plurality of shallow trenches
10
a
-
10
c
being formed on a silicon substrate
12
. After this, a deep trench
14
is formed within the shallow trench
10
b
in this particular case. The entire surface of the silicon substrate
12
is then covered with a BPSG (boro-phospho-silicate glass) film
16
using a CVD (chemical vapor deposition) technique. The BPSG film
16
is advantageous in that it has a coefficient of thermal expansion that is similar to that of the silicon substrate
12
. In addition, the BPSG film
16
is easily flattened by way of a reflow process.
As shown in
FIG. 1B
, the BPSG film
16
is etched back so as to leave the BPSB film
16
in both the shallow trenches
10
a
-
10
c
and the deep trench
14
. The surface of the BPSG film
16
in the trenches is flattened using a reflow process at temperature between 900° C. and 1000° C. for 30 to 60 minutes. Subsequently, as shown in
FIG. 1C
, a silicon oxide (SiO
2
) film
18
is deposited over the entire surface of the structure shown in FIG.
1
B. Thereafter, the silicon oxide film
18
is polished until the structure shown in
FIG. 1D
is obtained. Thus, the BPSG film
16
is effectively capped with the silicon oxide film
18
.
The aforesaid conventional technique, however, has suffered from the following drawbacks.
As mentioned above, the shallow trench is used to isolate MOS devices (transistors). A first drawback is described with reference to FIG.
2
. As shown in
FIG. 2
, the source, drain and gate regions
20
,
22
and
24
of a MOS transistor are provided in the immediate vicinity of the shallow trench
26
. Thus, boron (or phosphorus) contained in the BPSG film
16
(
FIG. 1
) is liable to diffuse into these regions
20
,
22
and
24
during thermal treatments for fabricating the transistors. That is to say, the diffusion of boron (or phosphorous) develops diffused regions, each of which exhibits a concentration of impurity equal to or more than that of a well. The concentration of each of the diffused layers depends on the volume of the associated shallow trench. Therefore, the diffused layers may exhibit different impurity concentrations with different locations on the substrate. Especially, the differences of diffused impurity concentrations under the gates, undesirably lead to the differences of threshold voltages with different devices.
On the other hand, the deep trench is used to isolate bipolar transistors. The BPSG film is filled in a deep trench and thus causes the following problem. For example, when an NPN transistor is fabricated, a N-type collector region and N-type buried layer are provided vertically and surrounded by the deep trench. In this case, since the concentration of boron in the BPSG film is higher than that of phosphorous, a P-type diffused layer is formed around the deep trench. As a result, parasitic capacitance is developed between the P-type diffused layer and the N-type collector region and between the P-type diffused layer and the N-type buried layer. This parasitic capacitance adversely affects the high-speed operations of the bipolar transistors. It is therefore highly desirable to suppress the formation of the parasitic capacitance.
Still further, as mentioned above, after the BPSG film
16
is removed (FIGS.
1
A and
1
B), the silicon oxide film
18
is removed (FIGS.
1
C and
1
D). That is, two times of film removal are necessary with the conventional technique. It is known in the art that the film removal is implemented frequently monitoring the thickness of the film on the substrate and accordingly, it is very difficult to automate such a process. Therefore, it is quite preferable if the number of times of removing the film is reduced to once.
SUMMARY OF THE INVENTION
It is therefore an object of the present to provide a technique that is able to markedly reduce the variations of threshold voltages of MOS transistors and the parasitic capacitance of bipolar transistors, which have been described in the above.
In brief, these objects are achieved by a technique wherein in order to isolate a plurality of MOS and bipolar devices provided on the same chip, a plurality of first and second trenches are provided on a semiconductor substrate. Each of the first trenches is filled with silicon oxide containing no impurity and is used to isolate the MOS devices. On the other hand, the second trenches are formed within the first trenches. Each second trench is filled silicon oxide containing phosphorous and boron and is used to isolate the bipolar devices. The inner surface of each second trench is coated with a silicon nitride film for preventing boron (or phosphorus) from being diffused into the surrounding region.
One aspect of the present invention resides in a semiconductor circuit comprising: a plurality of first trenches each of which is formed on a semiconductor substrate and is filled with a first dielectric film; and a plurality of second trenches each of which is formed in the first trench and filled with a second dielectric film.
Another aspect of the present invention resides in a semiconductor circuit comprising: a plurality of first trenches each of which is formed on a semiconductor substrate and is filled with first silicon oxide containing no impurity; and a plurality of second trenches each of which is formed in the first trench and filled with second silicon oxide containing phosphorous and boron.
Another aspect of the present invention resides in a semiconductor circuit comprising: a plurality of first trenches each of which is filled with first silicon oxide containing no impurity; a plurality of second trenches each of which is formed in the first trench and filled with second silicon oxide containing phosphorous and boron; and a barrier layer for preventing diffusion of phosphorous and boron from the second silicon oxide, the barrier layer being provided on an inner surface of each of the second trenches.
Still another object of the present invention resides in a semiconductor circuit comprising a plurality of MOS and bipolar devices on the same chip, the semiconductor circuit comprising: a plurality of first trenches each of which is formed on a semiconductor substrate and is filled with first silicon oxide containing no impurity, the first trenches being used to isolate the MOS devices; and a plurality of second trenches each of which is formed in the first trench and filled
Jones Josetta I.
Laff, Whitesel & Saret, Ltd.
Michael Best & Friedrich LLC
Niebling John F.
Whitesel J. Warren
LandOfFree
Semiconductor circuit using trench isolation and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor circuit using trench isolation and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor circuit using trench isolation and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2967865