Semiconductor circuit having improved layout pattern

Electronic digital logic circuitry – Significant integrated structure – layout – or layout... – Field-effect transistor

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257369, 257390, H01L 2500

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054898609

ABSTRACT:
A semiconductor circuit includes a plurality of first power supply lines which are arranged parallel to each other, a plurality of second power supply lines which are arranged parallel to each other and supplying a power supply voltage different from that supplied by the first power supply lines, where the first and second power supply lines run parallel to each other in a first direction, a first cell made up of the same number of first p-channel transistors and first n-channel transistors which are respectively coupled to the first and second power supply lines, where the first p-channel transistors and the first n-channel transistors are alternately arranged in a second direction and have the same size, and a second cell made up of a different number of second p-channel transistors and second n-channel transistors which are respectively coupled to the first and second power supply lines. The second p-channel transistors and the second n-channel transistors are alternately arranged in the second direction, and the second p-channel transistors are electrically coupled in parallel, so that the second p-channel transistors have a predetermined driving capability.

REFERENCES:
patent: 4771327 (1988-09-01), Usui
patent: 4825273 (1989-04-01), Arakawa
patent: 5038192 (1991-08-01), Bonneau
patent: 5175605 (1992-12-01), Pavlu
Patent Abstracts of Japan, vol. 13, No. 155 (E-743) (3503), Apr. 14, 1989 & JP-A-63 313835 (Mitsubishi Electric Corp.), Dec. 21, 1988.
Patent Abstracts of Japan, vol. 16, No. 11 (E-1153), Jan. 13, 1992 & JP-A-03 231462 (Horikoshi Kengo), Oct. 15, 1991.

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