Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-16
2002-05-14
Christian, Keith (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S240000, C438S261000, C438S253000
Reexamination Certificate
active
06387748
ABSTRACT:
TECHNICAL FIELD
The invention pertains to semiconductor circuit constructions, such as, for example capacitor constructions, and to methods of forming semiconductor circuit constructions. In particular aspects, the invention pertains to diffusion barrier layers for use in capacitor constructions.
BACKGROUND OF THE INVENTION
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. Yet as feature size continues to become smaller and smaller, development of improved materials for cell dielectrics as well as the cell structure are important. The feature size of 256 Mb DRAMs is on the order of 0.25 micron, and conventional dielectrics such as SiO
2
and Si
3
N
4
might not be suitable because of small dielectric constants.
Some dielectric materials considered to be promising as cell dielectrics layers are Ta
2
O
5
, barium strontium titanate (BST) and lead zirconate titanate (PZT). Such materials can be formed by, for example, chemical vapor deposition (CVD). The dielectric constant of Ta
2
O
5
, BST and PZT materials can be quite high. For instance, the dielectric constant of Ta
2
O
5
is approximately three times that of Si
3
N
4
. Proposed prior art capacitor constructions include the use of Ta
2
O
5
, PZT or BST as a capacitor dielectric layer, in combination with an overlying predominately crystalline TiN electrode or other layer. However, diffusion relative to the Ta
2
O
5
, PZT or BST layer can be problematic in the resultant capacitor construction. For example, tantalum and oxygen can undesirably out-diffuse from a Ta
2
O
5
-comprising dielectric layer; lead, zirconium, tantalum or oxygen can out-diffuse from a PZT-comprising dielectric; and one or more of barium, strontium and oxygen can undesirably out-diffuse from a BST-comprising dielectric layer. Further, materials from the adjacent conductive capacitor plates can diffuse into the Ta
2
O
5
, PZT or BST dielectric layer. The above-discussed diffusion into and out of Ta
2
O
5
, PZT and BST dielectric layers can cause electrical and other properties of the layers and the surrounding materials to be adversely affected in a less than predictable or an uncontrollable manner.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses a semiconductor circuit construction including a material which comprises Q, R, S and B. In such construction, Q comprises one or more refractory metals, R is selected from the group consisting of one or more of tungsten, aluminum and silicon, S is selected from the group consisting of one or more of nitrogen and oxygen, and B is boron. Also, in such construction R includes at least one element that is not included by Q.
In another aspect, the invention encompasses a method of forming a capacitor. A first capacitor electrode is formed, a diffusion barrier layer is formed proximate the first capacitor electrode, and a dielectric layer is formed to be separated from the first capacitor electrode by the diffusion barrier layer. A second capacitor electrode is formed to be separated from the first electrode by the dielectric layer. The diffusion barrier layer comprises Q
x
R
y
S
z
wherein Q is a refractory metal, R is selected from the group consisting of tungsten, aluminum and silicon, and S is selected from the group consisting of nitrogen and oxygen; provided that R includes at least one element that is not included by Q. The formation of the diffusion barrier layer comprises depositing the Q
x
R
y
S
z
and exposing the Q
x
R
y
S
z
to a nitrogen-containing plasma.
In yet another aspect, the invention encompasses a capacitor construction having a first capacitor electrode comprising Q
x
R
y
S
z
(B). In such construction, Q is a refractory metal; R is selected from the group consisting of tungsten, aluminum and silicon; S is nitrogen; and B is boron. In such construction, R includes at least one element that is not included by Q.
In yet another aspect, the invention encompasses a capacitor construction comprising a polysilicon-comprising interconnect, a diffusion barrier layer against the polysilicon-comprising interconnect, and a first capacitor electrode separated from the polysilicon-comprising interconnect by the diffusion barrier layer. The diffusion barrier layer comprises Q
x
R
y
S
z
; wherein Q is a refractory metal, R is selected from the group consisting of tungsten, aluminum and silicon, and S is selected from the group consisting of nitrogen and oxygen. The capacitor construction further comprises a dielectric layer proximate the first capacitor electrode, and a second capacitor electrode separated from the first electrode by the dielectric layer.
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Christian Keith
Kebede Brook
Micro)n Technology, Inc.
Wells St. John P.S.
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