Semiconductor circuit apparatus and test method thereof

Details Semiconductor circuit apparatus and test method thereof Semiconductor circuit apparatus and test method thereof

2007-07-10

2007-07-10

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000

Reexamination Certificate

active

10918497

ABSTRACT:
In a semiconductor circuit apparatus and its test method according to embodiments of the present invention, the clock enable control circuit can generate in a test mode an enable clock signal by using the substitute enable signal instead of the enable signal output from the enable signal generation combinational circuit and supplies it to the enable input terminal of the sequential circuit. Accordingly, with the simple structure in which the substitute enable signal is used, a proper enable clock signal can be generated and a scan test can be performed by reliably setting the sequential circuit to the enable state.

REFERENCES:
patent: 5519714 (1996-05-01), Nakamura et al.
patent: 5774702 (1998-06-01), Mitsuishi et al.
patent: 5848075 (1998-12-01), Katayama et al.
patent: 5918003 (1999-06-01), Koch et al.
patent: 2002/0112199 (2002-08-01), Whetsel
patent: 2002-323540 (2002-08-01), None

Affiliated with

Also associated with

Rating

Semiconductor circuit apparatus and test method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor circuit apparatus and test method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor circuit apparatus and test method thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3744707