Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2005-06-07
2005-06-07
Cao, Chun (Department: 2115)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S502000, C327S297000
Reexamination Certificate
active
06904536
ABSTRACT:
The burden of developing a complex bridge block imposed on the IP reuser is reduced by introducing a system clock into the IP. The IP composed of a functional circuit of this invention and its synchronizing circuit takes in the system clock by integrating the synchronizing circuit taking in the system clock with the IP functional circuit into the IP in reusing the IP complying with the standard in the development of an LSI with a built-in IP and its derivatives. This enables the reuser to incorporate the IP into the LSI via a simple bridge block, taking into account only the system clock for driving the system bus, which reduces the burden of handling the IP and increases the reusability of the IP.
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Japanese Office Action dated Oct. 1, 2004 corresponding to Japanese Paten Application No. 2000-196868 and an English translation of same.
Cao Chun
Kabushiki Kaisha Toshiba
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