Semiconductor chips with crack stop regions for reducing...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Solder wettable contact – lead – or bond

Reexamination Certificate

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C257SE23081

Reexamination Certificate

active

07732932

ABSTRACT:
Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically coupled to the N interconnect layers. The structure further includes a first dielectric layer on top of the N interconnect layers and P crack stop regions on top of the first dielectric layer, P being a positive integer. The structure further includes a second dielectric layer on top of the first dielectric layer. Each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer. The structure further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer.

REFERENCES:
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patent: 7256474 (2007-08-01), Wakayama et al.
patent: 7339256 (2008-03-01), Nakamura et al.
patent: 7482675 (2009-01-01), Adkisson et al.
patent: 2005/0285229 (2005-12-01), Higashi et al.
patent: 2006/0012012 (2006-01-01), Wang et al.
patent: 2007/0040242 (2007-02-01), Sasaki et al.
patent: 2009/0032929 (2009-02-01), Daubenspeck et al.
patent: 2009/0194850 (2009-08-01), Kaltalioglu et al.

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